TC58NVG2S3ETA00 Datasheet, PDF (32/70 Pages) Toshiba Semiconductor – 4 GBIT (512M x 8 BIT) CMOS NAND E2PROM

TC58NVG2S3ETA00
DEVICE OPERATION
Read Mode
Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the two
commands, a start address for the Read mode needs to be issued. Refer to the figures below for the sequence and
the block diagram (Refer to the detailed timing chart.).
CLE
CE
WE
ALE
RE
RY / BY
Column Address M Page Address N
Busy
t_R
I/O
00h
M
Data Cache
Page Buffer
Select page
N
30h
M
M+1 M+2
Start-address input
m
I/O1 to 8: m = 2111
Cell array
Page Address N
A data transfer operation from the cell array to the Data
Cache via Page Buffer starts on the rising edge of WE in the
30h command input cycle (after the address information has
been latched). The device will be in the Busy state during this
transfer period.
After the transfer period, the device returns to Ready state.
Serial data can be output synchronously with the RE clock
from the start address designated in the address input cycle.
Random Column Address Change in Read Cycle
CLE
CE
WE
ALE
RE
RY / BY
I/O ^00h
Busy
t_R
Col. M
30h
M _{M+1 M+2 M+3} 05h
E0h _{M’ M’+1 M’+2 M’+3 M’+4}
Col. M
Page N
Start-address input
M
M’
Select page
N
Page N
Start from Col. M
Col. M’
Page N
Start from Col. M’
During the serial data output from the Data Cache, the column
address can be changed by inputting a new column address
using the 05h and E0h commands. The data is read out in serial
starting at the new column address. Random Column Address
Change operation can be done multiple times within the same
page.
32
2012-09-01