TC58NVG2S3ETA00 Datasheet, PDF (19/70 Pages) Toshiba Semiconductor – 4 GBIT (512M x 8 BIT) CMOS NAND E2PROM

Auto-Program Operation with Data Cache Timing Diagram (3/3)
TC58NVG2S3ETA00
CLE
CE
t_CLS
t_CLS tCLH
t_CS
t_CS
t_CH
WE
t_ALH
t_ALS
ALE
t_ALH
t_ALS
t_{PROG (*1)}
t_WB
RE
I/O
RY / BY
t_{DS tDH}
80h
t_DS t_DH
CA0 CA8 PA0 PA8 PA16
to 7 to 11 to 7 to 15 _{to 17}
t_DS
t_DH
D_INN
D_IN
N+1
10h
D_IN2111
: Do not input data while data is being output.
: V_IH or V_IL
t_DS
t_DH
70h
Status
2
Continued from 2 of last page
(*1) t_PROG: Since the last page programming by 10h command is initiated after the previous cache
program, the t_PROG during cache programming is given by the following equation.
t_PROG = t_PROG of the last page + t_PROG of the previous page − A
A = (command input cycle + address input cycle + data input cycle time of the last page)
If “A” exceeds the t_PROG of previous page, t_PROG of the last page is t_PROG max.
(Note)
Make sure to terminate the operation with 80h-10h- command sequence.
If the operation is terminated by 80h-15h command sequence, monitor I/O 6 (Ready / Busy) by
issuing Status Read command (70h) and make sure the previous page program operation is
completed. If the page program operation is completed issue FFh reset before next operation.
19
2012-09-01