TC58NVG2S3ETA00 Datasheet, PDF (51/70 Pages) Toshiba Semiconductor – 4 GBIT (512M x 8 BIT) CMOS NAND E2PROM

TC58NVG2S3ETA00
EDC Operation
Note that for the user who use Copy-Back with EDC mode, only one time random data input is available at the
same address during Copy-Back program or page program mode. For the user who Copy-Back without EDC,
there is no limitation for the random data input at the same address.
Copy-Back Program Operation with EDC & Read EDC Status
tR
tPROG
R/ B
I/Ox
00h
Add.(5Cycles) 35h
Col. Add.1,2 & Row Add.1,2,3
Source Address
85h
Add.(5Cycles) 10h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
7Bh EDC Status Output
Multi Page Copy-Back Program Operation with EDC & Read EDC Status
tR
R/ B
I/Ox
60h
Add.(3Cycles)
60h
Add.(3Cycles)
35h
Row Add.1,2,3
Source Address
Row Add.1,2,3
Destination Address
tDCBSYW1
tPROG
R/ B
I/Ox
85h
Add.(5Cycles) 11h
Col. Add.1,2 & Row Add.1,2,3
Source Address
81h
Add.(5Cycles) 10h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
7Bh EDC Status Output
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2012-09-01