TC55VZM216A Datasheet, PDF (5/11 Pages) Toshiba Semiconductor – 262,144-WORD BY 16-BIT CMOS STATIC RAM

TC55VZM216AJJN/AFTN08,10,12
AC CHARACTERISTICS (Ta = 0° to 70°C ^{(See Note 1)}, V_DD = 3.3 V ± 0.3 V)
READ CYCLE
SYMBOL
t_RC
t_ACC
t_CO
t_OE
t_BA
t_OH
t_COE
t_OEE
t_BE
t_COD
t_ODO
t_BD
TC55VZM216AJJN/AFTN
PARAMETER
08
10
12
MIN MAX MIN MAX MIN MAX
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Upper Byte, Lower Byte Access Time
Output Data Hold Time from Address Change
8

10

12


8

10

12

8

10

12

4

5

6

4

5

6
3

3

3

Output Enable Time from Chip Enable
3

3

3

Output Enable Time from Output Enable
0

0

0

Output Enable Time from Upper Byte, Lower Byte 0

0

0

Output Disable Time from Chip Enable

4

5

6
Output Disable Time from Output Enable

4

5

6
Output Disable Time from Upper Byte, Lower Byte 
4

5

6
UNIT
ns
WRITE CYCLE
SYMBOL
PARAMETER
t_WC
t_WP
t_CW
t_BW
t_AW
t_AS
t_WR
t_DS
t_DH
t_OEW
t_ODW
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Upper Byte, Lower Byte Enable to End of Write
Address Valid to End of Write
Address Setup Time
Write Recovery Time
Data Setup Time
Data Hold Time
Output Enable Time from Write Enable
Output Disable Time from Write Enable
TC55VZM216AJJN/AFTN
08
10
12
MIN MAX MIN MAX MIN MAX
8

10

12

6

7

8

6

7

8

6

7

8

6

7

8

0

0

0

0

0

0

4

5

6

0

0

0

3

3

3


4

5

6
UNIT
ns
AC TEST CONDITIONS
PARAMETER
Input Pulse Level
Input Pulse Rise and Fall Time
Input Timing Measurement
Reference Level
Output Timing Measurement
Reference Level
Output Load
TEST CONDITION
3.0 V/ 0.0 V
2 ns
1.5 V
1.5 V
Fig.1
Fig.1
I/O pin ^Z0 ^{= 50 Ω}
3.3 V
I/O pin
1200 Ω
C_L = 30 pF
R_L = 50 Ω
C_L = 5 pF
870 Ω
V_L = 1.5 V
(For t_COE, t_OEE, t_BE, t_COD,
t_BD, t_ODO, t_OEW and t_ODW)
2003-01-17 5/11