TA1317ANG Datasheet, PDF (49/59 Pages) Toshiba Semiconductor – Deflection Processor IC for TV

TA1317ANG
Note
No.
32
Parameter
SW5
Vertical DF phase adjustment OFF
(V DF phase)
SW6
B
SW7
ON
Test Condition
SW Mode
SW8 SW10 SW11 SW17 SW24
Test Method
(unless otherwise specified, V_CC = 9 V, Ta = 25 ± 3°C, data = preset values)
OFF B
ON
A
A (1) Input vertical trigger pulse to pin V_IN.
Pulse level (VT) = 3.0 V
(2) Set V-DF PHASE (sub-address: 06) to minimum (data: 08) and measure pin 18
(V-DF OUT) phase T_VD (08).
(3) Set V-DF PHASE (sub-address: 06) to maximum (data: F8) and measure pin 18
(V-DF OUT) phase T_VD (F8).
(4) Calculate change amount T_VD using the following formula.
33 LVP detection voltage
34 Vertical guard detection
voltage
OFF
B
ON OFF B
ON
B
OFF C
ON OFF B
ON
A
T_VD (08) T_VD (F8)
Pin 18 (V-DF OUT) waveform
T_VD = T_VD (08) + T_VD (F8)
A (1) Connect external supply voltage V₇ to TP17 (LVP).
(2) Decrease external supply voltage V₇ from 9 V. When D5 data in Read mode
changes from 0 to 1, measure TP17 voltage V_LVP.
A (1) Connect external supply voltage V₆ to TP6 (V NF).
(2) Switch to VD (sub-address: 00) to AC-Coupling mode (data: 81).
(3) Increase external supply voltage V₆ from 5.5 V. When D3 data in Read mode
changes from 0 to 1, measure TP6 voltage V_VGH.
(4) Decrease external supply voltage V₆ from 5.5 V. When D3 data in Read mode
changes from 0 to 1, measure TP6 voltage V_VGL.
49
2005-08-18