TA1317ANG Datasheet, PDF (28/59 Pages) Toshiba Semiconductor – Deflection Processor IC for TV

TA1317ANG
Note
No.
8
Parameter
Vertical phase adjustment 2
(V centering) change amount
SW5
ON
SW6
A
SW7
OFF
Test Condition
SW Mode
SW8 SW10 SW11 SW17 SW24
Test Method
(unless otherwise specified, V_CC = 9 V, Ta = 25 ± 3°C, data = preset values)
OFF B
ON
A
A (1) Input vertical trigger pulse to pin V_IN.
Pulse level (VT) = 3.0 V
(2) Set VD (sub-address: 00) to DC-Coupling mode (data: 80).
(3) Set V INTEGRAL CORRECTION (sub-address: 08) to center (data: 88).
(4) Set V S CORRECTION (sub-address: 09) to center (data: A0).
(5) Set V CENTERING (sub-address: 05) to minimum (data: 00) and measure V_DD (00)
as shown in the figure below.
(6) Set V CENTERING (sub-address: 05) to maximum (data: FE) and measure V_DD
(FE) as shown in the figure below.
(7) Calculate change amount V_DD using the following formula.
Pin 6
(V NF) waveform
V_DD (FE)
V_DD (00)
V_DD = V_DD (FE) − V_DD (00)
10 ms
10 ms
28
2005-08-18