TH50VSF3583AASB Datasheet, PDF (44/50 Pages) Toshiba Semiconductor – TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS

TH50VSF3582/3583AASB
SRAM DATA RETENTION CHARACTERISTICS (Ta = -30°~85°C)
SYMBOL
PARAMETER
MIN
V_DH
Data Retention Supply Voltage for SRAM
I_CCS4
V_DH = 3.3 V Ta = −30°~85°C
SRAM Standby Current
Ta = −30°~40°C
V_DH = 3.0 V
Ta = −30°~85°C
t_CDR
Chip-Deselect-to-Data-Retention-Mode Time
t_r
Recovery Time
(1) Read cycle time
1.5



0
t_RC(1)
CE1S-CONTROLLED DATA RETENTION MODE (see Note 1)
TYP.






MAX
3.3
10
1
5


UNIT
V
µA
ns
ns
V_CCs
V_CCs
2.7 V
Data Retention Mode
V_IH
CE1S
(See Note 2)
t_CDR
V_CCs − 0.2 V
(See Note 2)
t_r
GND
CE2S-CONTROLLED DATA RETENTION MODE (see Note 3)
V_CCs
V_CCs
2.7 V
Data Retention Mode
CE2S
V_IH
t_CDR
t_r
V_IL
GND
0.2 V
Notes:
(1)
(2)
(3)
In CE1S -Controlled Data Retention Mode, Minimum Standby Current Mode is entered when
CE2S ≤ 0.2 V or CE2S ≥ VCCs − 0.2 V.
When CE1S is operating at the VIH level, the SRAM standby current is the same as ICCS3 during the
transition of VCCs from 2.67 V to 2.3 V.
In CE2S-Controlled Data Retention Mode, Minimum Standby Current Mode is entered when
CE2S ≤ 0.2 V.
2001-06-08 44/50