TH50VSF3583AASB Datasheet, PDF (18/50 Pages) Toshiba Semiconductor – TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS

COMMAND WRITE/PROGRAM/ERASE CYCLE
SYMBOL
PARAMETER
t_CMD
t_AS
t_AH
t_AHW
t_DS
t_DH
t_WELH
t_WEHH
t_CES
t_CEH
t_CELH
t_CEHH
t_WES
t_WEH
t_OES
t_OEHP
t_OEHT
t_BEH
t_VCS
t_BUSY
t_RP
t_READY
t_RB
t_RH
t_CEBTS
t_SUSP
t_RESP
t_SUSE
t_RESE
Command Write Cycle Time
Address Set-up Time / BYTE Set-up Time
Address Hold Time / BYTE Hold Time
Address Hold Time from WE High level
Data Set-up Time
Data Hold Time
WE Low-Level Hold Time
( WE Control)
WE High-Level Hold Time
( WE Control)
CEF Set-up Time to WE Active ( WE Control)
CEF Hold Time from WE High Level( WE Control)
CEF Low-Level Hold Time
( CEF Control)
CEF High-Level Hold Time
( CEF Control)
WE Set-up time to CEF Active
( CEF Control)
WE Hold Time from CEF High Level( CEF Control)
OE Set-up Time
OE Hold Time (Toggle, Data Polling)
OE High-Level Hold Time (Toggle)
Erase Hold Time
V_CCf Set-up Time
Program/Erase Valid to RY/BY Delay
RESET Low-Level Hold Time
RESET Low-Level to Read Mode
RY/BY Recovery Time
RESET Recovery Time
CEF Set-up time BYTE Transition
Program Suspend Command to Suspend Mode
Program Resume Command to Program Mode
Erase Suspend Command to Suspend Mode
Erase Resume Command to Erase Mode
TH50VSF3582/3583AASB
LOAD CAPACITANCE
30pF
100pF
MIN
MAX
MIN
MAX
70

80

0

0

40

40

20

20

40

40

0

0

40

40

20

20

0

0

0

0

40

40

20

20

0

0

0

0

0

0

90

90

20

20

50

50

500

500


90

90
500

500


20

20
0

0

50

50

5

5


1.5

1.5

1

1

15

15

1

1
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
ns
ns
ns
µs
µs
µs
µs
2001-06-08 18/50