TH50VSF3583AASB Datasheet, PDF (23/50 Pages) Toshiba Semiconductor – TOSHIBA MULTI-CHIP INTEGRATED CIRCUIT SILICON GATE CMOS

Program Suspend / Resume Mode
TH50VSF3582/3583AASB
Program Suspend is used to enable Data Read by suspending Write operation. The device receives a Program
Suspend command in Write mode (including Write performed during Erase Suspend) but ignores the command
in other modes. At command input, the address of the bank on which Write is being performed must be specified.
After command input, the device enters Program Suspend Read mode after tSUSP.
During Program Suspend, Cell Data Read, ID Read and CFI Data Read can be performed. When Data Write
is suspended, the address to which Write was being performed becomes undefined. ID Read and CFI Data Read
are the same as usual.
After completion of Program Suspend, to return to Write mode, input a Program Resume command. At
command input, specify the address of the bank on which Write is being performed. When the ID Read and CFI
Data Read functions are used, end the functions before inputting the Resume command. On receiving the
Resume command, the device returns to Write mode and resumes output of a Hardware Sequence flag from the
bank to which data are being written.
Program Suspend can be run in Fast Program or Acceleration mode. However, note that when running
Program Suspend in Acceleration mode, do not release VACC.
Auto Chip Erase Mode
The Auto Chip Erase mode is set using the Chip Erase command. The Auto Chip Erase operation starts on
the rising edge of WE in the sixth bus cycle. All memory cells are automatically preprogrammed to 0, erased
and verified as erased by the chip. The device status is determined from the Hardware Sequence flag.
Command inputs are ignored during an Auto Chip Erase. The hardware reset allows interruption of an Auto
Chip Erase operation. The Auto Chip Erase operation does not complete correctly when interrupted. Hence a
further Erase operation is necessary.
An attempt to erase a protected block is ignored. If all blocks are protected, the Auto Erase operation will not
be executed and the device will enter Read mode 100 µs after the rising edge of the WE signal in the sixth bus
cycle.
If an Auto Chip Erase operation fails, the device remains in, erasing state and does not return to Read mode.
The device status is determined from the Hardware Sequence flag. Either a Reset command or a hardware reset
is necessary to return the device to Read mode after a failure.
In this case, the block in which a failure occurred cannot be detected. Either terminate device usage, or
perform Block Erase for each block, specify the failed block, and stop using it. The host processor must take
measures to prevent use of the failed block being used in the future.
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