TMP92CH21FG Datasheet, PDF (415/540 Pages) Toshiba Semiconductor – CMOS 32-Bit Microcontroller

TMP92CH21
3.18.2 Operation of Each Block
(1) Prescaler
The 5-bit prescaler generates the source clock for timer 0. The prescaler clock (φT0) is
a divided clock (divided by 8) from the f_FPH.
This prescaler can be started or stopped using TB0RUN<TB0PRUN>. Counting
starts when <TB0PRUN> is set to 1; the prescaler is cleared to 0 and stops operation
when <TB0PRUN> is cleared to 0.
System clock
selection
SYSCR1
<SYSCK>
1 (fs)
0 (fc)
Table 3.18.2 Prescaler Clock Resolution
Clock gear
selection
SYSCR1
−
<GEAR2:0>
Timer counter input clock
TMRB prescaler
TB0MOD<TB0CLK1:0>
φT1(1/2)
φT4(1/8) φT16(1/32)
−
000 (1/1)
001 (1/2)
1/8
010 (1/4)
011 (1/8)
100 (1/16)
fs/16
fc/16
fc/32
fc/64
fc/128
fc/256
fs/64
fc/64
fc/128
fc/256
fc/512
fc/1024
fs/256
fc/256
fc/512
fc/1024
fc/2048
fc/4096
XXX: Don't care
(2) Up counter (UC10)
UC10 is a 16-bit binary counter which counts up pulses input from the clock specified
by TB0MOD<TB0CLK1:0>.
Any one of the prescaler internal clocks φT1, φT4 and φT16 can be selected as the
input clock. Counting or stopping and clearing of the counter is controlled by
TB0RUN<TB0RUN>.
When clearing is enabled, the up counter UC10 will be cleared to 0 each time its
value matches the value in the timer register TB0RG1H/L. If clearing is disabled, the
counter operates as a free-running counter.
Clearing can be enabled or disabled using TB0MOD<TB0CLE>.
A timer overflow interrupt (INTTBOF0) is generated when UC10 overflow occurs.
92CH21-413
2007-02-28