TMP92CH21FG Datasheet, PDF (334/540 Pages) Toshiba Semiconductor – CMOS 32-Bit Microcontroller

TMP92CH21
LCD Size Setting Register
LCDSIZE
(0284H)
7
6
5
Bit symbol
Read/Write
After reset
Function
COM3
COM2
COM1
R/W
R/W
R/W
0
0
0
Common setting
0000: Reserved 0101: 200
0001: 64
0110: 240
0010: 120
0111: 320
0011: 128
1000: 480
0100: 160
Others: Reserved
4
COM0
R/W
0
3
2
SEG3
SEG2
R/W
R/W
0
0
Segment setting
0000: Reserved 0101: 320
0001: 64
0110: 480
0010: 128
0111: 640
0011: 160
1000: 768
0100: 256
1001: 960
1
SEG1
R/W
0
0
SEG0
R/W
0
Others: Reserved
Note 1: Maximum size in color mode (STN,TFT) is 320 × 320.
When internal SRAM is set as display RAM, the maximum size is as below.
1 bpp (Monochrome): 640 × 200
2 bpp (4 grayscales): 320 × 200
4 bpp (16 grayscales): 256 × 128
8 bpp (256 colors): 128 × 128
12 bpp (4096 colors): 128 × 64
Note 2: This LSI does not support 240-segment size, but if a cascade type segment driver is selected, it can used
by setting for 256-segment size. In this case, a 256-segment display area must be prepared.
LCD Control-0 Register
7
6
5
4
3
2
1
0
LCDCTL0
(0285H)
Bit symbol
Read/Write
After reset
Function
ALL0
FRMON
R/W
R/W
0
0
Column
Frame
data setting ^divide
0: Normal ^setting
1: All display ^{0: Disable}
data “0” ^{1: Enable}
−
R/W
0
Always
write “0”.
FP9
R/W
0
f_FP setting
bit9
MMULCD
FP8
R/W
R/W
0
0
Built-in RAM fFP setting
LCD driver bit8
setting
0: Sequential
access
1: Random
access
START
R/W
0
LCDC start
0: Stop
1: Start
LCD Control-1 Register
7
6
5
4
3
LCDCTL1 Bit symbol LCP0P
(0286H)
Read/Write
R/W
LCP1P
R/W
LBCDP
R/W
After reset
1
0
1
Function
LCP0 phase LCP1 phase LBCD phase
0: Rise
0: Rise
0: Low
1: Fall
1: Fall
enable
1: High
enable
2
1
0
LBCDW1 LBCDW0
R/W
R/W
0
0
LBCD width control
00 : LCP1_1CLK
01 : LCP1_2CLK
10 : LCP1_3CLK
11 : Reserved
LCDSCC
(0287H)
Bit symbol
Read/Write
After reset
Function
7
SCC7
0
LCDC Source Clock Counter Register
6
5
4
3
2
SCC6
0
SCC5
SCC4
SCC3
SCC2
R/W
0
0
0
0
LCDC source clock counter bit7 to bit0
1
SCC1
0
0
SCC0
0
92CH21-332
2007-02-28