TMP92CH21FG Datasheet, PDF (104/540 Pages) Toshiba Semiconductor – CMOS 32-Bit Microcontroller

TMP92CH21
3.5.16 Port L (PL0 to PL7)
PL0 to PL3 are 4-bit output ports. Resetting sets the output latch PL to “0”, and PL0 to
PL3 pins output “0”.
PL4 to PL7 are 4-bit general-purpose I/O ports. Each bit can be set individually for input
or output using the control register PLCR. Resetting resets the control register PLCR to “0”
and sets PL4 to PL7 to input ports. In addition to functioning as a general-purpose I/O port,
port L can also function as a data bus for an LCD controller (LD0 to LD7). The above
settings are made using the function register PLFC.
Reset
Function control
PLFC write
R
Output latch
PL write
LD0 to LD3
S
A
Selector
B
PL read
Figure 3.5.43 Register for Port L0 to L3
Reset
Direction control
PLCR write
Function control
PLFC write
S
Output latch
PL write
LD4 to LD7
PL read
S
A
Selector
B
S
B
Selector
A
Figure 3.5.44 Register for Port L4 to L7
92CH21-102
PL0 to PL3 (LD0 to LD3)
PL4 to PL7 (LD4 to LD7)
2007-02-28