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| TC94A09F Datasheet, PDF (4/19 Pages) Toshiba Semiconductor – Single-Chip CD Processor with Built-in Controller | |||
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Block Diagram
TC94A09F
VREF
XVSS
XI
XO
XVDD
DVSR
RO
DVRR
DVDD
DVRL
LO
DVSL
Clock gene.
CD clock
PWM
DA
VREF
ZDET
SERVO
control
AD
VREF
ROM
RAM
Digital equalizer
Automatic adjustment
circuit
CLV
servo
Sub code decoder
Synchronous
guarantee EFM
decode
Data
slicer
PLL
TMAX
VCO
VDD
Audio out
Digital out
16 k SRAM
VSS
P2-0~P2-3
IN1
CD Reset Correction circuit
MXO
MXI
P1-3 (K3)
P1-0 (K0)
Xâtal OSC
Port1
Timer
SBSY
INTR
Interrupt
Cont.
Serial
Interface
P4-3 (SCK/SCL)
P4-2 (SI0/SI1/SDA)
P4-1 (SI2)
P4-0 (Adin4/BUZR)
Port4
BUZR
MPX
CPU clock
Micon interface
SBSY
CLCK, DATA, SFSY,
LRCK, BCK, MBOV, IPF
Data Reg (16 bit)
ROM
(16 ´ 12288 Step)
G-Reg.
RAM
(4 ´ 512 word)
Program
Counter
Instruction
Decoder
OT19-22
R/W Buf.
ALU
F/F
P3-3 (Adin3)
P3-2 (Adin2)
P3-1 (Adin1)
P3-0
AD
Conv.
Port3
Stack Reg.
(8Level)
Reset
Power on Reset
Bias
ZDET, CLCK, DATA, SFSY, LRCK, BCK, MBOV, IPF
LCD Driver/Output Port
Port8
RFI
SLCO
TMAX
PDO
P2VREF
VCOF
PVREF
LPFO
LPFN
SBOK
SBSY
DOUT
OT22 (COFS)
OT21 (SPDA)
OT20 (SPCK)
OT19 ( HSO )
HOLD
TESTM
TESTC
IN1
IN2
P2-0 (EMPHin)
P2-1 (HSOin)
P2-2 (LRCKin)
P2-3 (DATAin)
RST
MVDD
MVSS
4
2001-10-15
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