TC59LM914AMG Datasheet, PDF (35/59 Pages) Toshiba Semiconductor – MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

MULTIPLE BANK WRITE TIMING (CL = 3)
TC59LM914/06AMG-37,-50
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
CLK
CLK
I_RBD = 2 cycles
I_RBD = 2 cycles I_RBD = 2 cycles I_RBD = 2 cycles I_RBD = 2 cycles
Command WRA LAL WRA LAL DESL WRA LAL WRA LAL WRA LAL WRA LAL WRA LAL WRA
Address UA LA UA LA
UA LA UA LA UA LA UA LA UA LA UA
Bank Add.
BL = 2
DQS/ DQS
(input)
Bank
"a"
Bank
"b"
Bank
"a"
I_RC (Bank"a") = 5 cycles
I_RC (Bank"b") = 5 cycles
WL = 2
WL = 2
Bank
"b"
Bank
"c"
Bank
"d"
Bank
"a"
Bank
"b"
DQ
(input)
Da0 Da1
Db0Db1
Da0Da1
Db0Db1
Dc0 Dc1
Dd0Dd1
BL = 4
DQS/ DQS
(input)
DQ
(input)
WL = 2
WL = 2
Da0Da1Da2Da3Db0Db1Db2Db3
Da0Da1Da2 Da3Db0Db1Db2Db3 Dc0 Dc1 Dc2 Dc3 Dd0 Dd1Dd2Dd3
Note: l_RC to the same bank must be satisfied.
TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20 35/59