TC59LM914AMG Datasheet, PDF (25/59 Pages) Toshiba Semiconductor – MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC

SINGLE BANK READ TIMING (CL = 5)
TC59LM914/06AMG-37,-50
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
CLK
CLK
I_RC = 6 cycles
I_RC = 6 cycles
Command RDA LAL
I_RCD=1 cycle
DESL
I_RAS = 5 cycles
RDA LAL
I_RCD=1 cycle
DESL
I_RAS = 5 cycles
RDA LAL
I_RCD=1 cycle
DESL
Address UA LA
UA LA
UA LA
Bank Add. #0
BL = 2
DQS/ DQS
Hi-Z
(output)
DQ
Hi-Z
(output)
BL = 4
DQS/ DQS
Hi-Z
(output)
DQ
Hi-Z
(output)
#0
#0
CL = 5
Q0 Q1
CL = 5
Q0 Q1
CL = 5
Q0 Q1 Q2 Q3
CL = 5
Q0 Q1 Q2 Q3
Note : TC59LM914AMG doesn’t have DQS .
Rev 1.0
2004-08-20 25/59