TMP1942CZUE Datasheet, PDF (327/406 Pages) Toshiba Semiconductor – 32bit TX System RISC

TMP1942CY/CZ
Table 3.13.1 Relationship Among A/D Conversion Modes, Interrupt Generation Timing and Flag Operation
Conversion Interrupt Generation EOCF Setting Timing ADBF (After Interrupt
ADMOD0
Mode
Timing
(*1)
is Generated) _{ITM1:0 REPEAT SCAN}
Channel-fixed After conversion has been After conversion has been
single conversion completed
completed
Channel-fixed
repeated
conversion
Every time one conversion Every time one conversion
has been completed
has been completed
Every time four conversions Every time four conversions
have been completed
have been completed
Every time eight conversions Every time eight conversions
have been completed
have been completed
Channel scan After scan conversion has After scan conversion has
single conversion been completed
been completed
Channel scan
repeated
conversion
Every time one scan
conversion has been
completed
Every time one scan
conversion has been
completed
0
1 (*2)
1 (*2)
1 (*2)
0
1 (*2)
⎯
0
0
00
01
1
0
10
⎯
0
1
⎯
1
1
(Note*1) EOCF is cleared when it is read.
(Note*2) If repeat intervals are used with RI set to 1, ADBF indicates 0 during interval periods.
ADMOD0<RI> can be used to control the time between one scan conversion being completed
and the next scan conversion being started (repeat interval). This bit is only effective when REPEAT
= 1.
Example: When repeated scan for channels AN0 to AN2 is set
Repeated scan conversions when RI = 0
Channel Converted
0
1
2
0
1
2
0
First Scan
Second Scan
Third Scan
Repeated scan conversions when RI = 1
Channel Converted
0
1
2
0
1
2
0
First Scan
Interval of 8 ADC
clock cycles
Second Scan
Note: If the start condition for highest-priority A/D conversion is satisfied during an interval period, highest-priority A/D
conversion is started immediately. Since the interval counter continues running during highest-priority A/D
conversion, the next scan will start when both of the following conditions are satisfied: an overflow of the
interval counter and the completion of highest-priority A/D conversion.
(5) Highest-priority conversion mode
Highest-priority A/D conversion can be performed by interrupting normal A/D conversion.
Highest-priority A/D conversion can be started either programmatically by setting
ADMOD2<HPADCE> to 1 or by using a hardware resource as specified with ADMOD4<7:6>. If
highest-priority A/D conversion is started during normal A/D conversion, the converter first stores
the result of the current conversion to the appropriate result register pair, and then performs a single
conversion for the channel specified with ADMOD2<3:0>. The result of that conversion is stored in
ADREGSP, at which point a highest-priority A/D conversion interrupt is generated. Then, normal
A/D conversion is resumed following the last conversion for which the result was stored. Any
condition that triggers highest-priority A/D conversion is ignored while highest-priority A/D
conversion is in progress.
For example, suppose channel scan repeated conversion is being performed for AN0 to AN8. If
HPADCE is set to 1 during conversion for AN3, the converter will wait for the conversion for AN3
TMP1942CY/CZ-326