TMP1942CZUE Datasheet, PDF (217/406 Pages) Toshiba Semiconductor – 32bit TX System RISC

TX1942CY/CZ
TB5FFCR
(0xFFFF_
F193)
TMRB5 flip-flop control register
7
6
5
4
3
2
1
0
Bit symbol
Read/Write
After reset
Function
⎯
⎯
W*
1
1
Must always be set to 11.
* These bits are always
11 when read.
TB5C1T1 TB5C0T1 TB5E1T1
R/W
0
0
0
TB5FF0 inversion trigger
0: Trigger disabled
1: Trigger enabled
When
up-counter
value is
latched into
TB5CP1
When
up-counter
value is
latched into
TB5CP0
When
up-counter
and
TB5RG1
values
match
TB5E0T1
0
When
up-counter
and
TB5RG0
values
match
TB5FF0C1 TB5FF0C0
W*
1
1
TB5FF0 control
00: Invert
01: Set
10: Clear
11: Don’t care
* These bits are always 11
when read.
Control of timer flip-flop (TB5FF0)
00 TB5FF0 value inverted (soft inversion)
01 TB5FF0 set to 1
10 TB5FF0 set to 0
11 Don’t care (read as 11)
Trigger for inverting timer flip-flop (TB5FF0) when
up-counter and TB5RG0 values match
0 Trigger disabled (inversion disabled)
1 Trigger enabled (inversion enabled)
Trigger for inverting timer flip-flop (TB5FF0) when
up-counter and TB5RG1 values match
0 Trigger disabled (inversion disabled)
1 Trigger enabled (inversion enabled)
Trigger for inverting timer flip-flop (TB5FF0) when
up-counter value is latched into TB5CP0
0 Trigger disabled (inversion disabled)
1 Trigger enabled (inversion enabled)
Trigger for inverting timer flip-flop (TB5FF0) when
up-counter value is latched into TB5CP1
0 Trigger disabled (inversion disabled)
1 Trigger enabled (inversion enabled)
Figure 3.10.21 TMRB Registers
TMP1942CY/CZ-216