TMP1942CZUE Datasheet, PDF (297/406 Pages) Toshiba Semiconductor – 32bit TX System RISC

TMP1942CY/CZ
INTS2 interrupt
if MST = 0
Then go to slave mode processing
if TRX = 0
Then go to receiver mode processing
if LRB = 0
Then go to processing for generating stop condition
SBI0CR1 ← X X X X 0 X X X
Set number of bits to be transferred and ACK.
SBI0DBR ← X X X X X X X X
Write transfer data.
End of interrupt processing
Note: X: Don't care
SCL pin
Write to SBI0DBR
SDA pin
<PIN>
1
2
3
4
5
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Ack signal
from receiver
INTS2 Interrupt Request
Master output
Slave output
Figure 3.12.13 Example in Which SBI0CR1<BC2:BC0> = 000 and SBI0CR1<ACK> = 1 (Transmitter Mode)
In receiver mode (when SBI0SR<TRX> = 0)
If the next data item to be transferred is 8 bits long, write the transfer data to SBI0DBR. If it
is not 8 bits long, set SBI0CR1<BC2:BC0> and SBI0CR1<ACK> and then read the received
data from SBI0DBR in order to release the SCL line. (The data read out immediately after the
transmission of the slave address is undefined.) When data is read from the data buffer register,
SBI0CR2<PIN> is set to 1. The serial clock for transferring the next word of data is output on
the SCL pin. The SDA pin is pulled Low at the final bit when the acknowledge signal goes
Low.
An INTS2 interrupt request is now generated, SBI0CR2<PIN> is reset to 0 and the SCL pin
is pulled Low. Each time received data is read from SBI0DBR, a clock pulse for one-word data
transfer and an acknowledge signal are output.
Read received data
SCL
1
2
3
4
5
6
7
8
9
SDA
<PIN>
D7
D6
D5
D4
D3
D2
D1
D0
ACK
Next D7
Ack signal to
transmitter
INTS2 Interrupt Request
Master output
Slave output
Figure 3.12.14 Example in Which SBI0CR1<BC2:BC0> = 000 and SBI0CR1<ACK> = 1 (Receiver Mode)
TMP1942CY/CZ-296