TMP1942CZUE Datasheet, PDF (321/406 Pages) Toshiba Semiconductor – 32bit TX System RISC

TMP1942CY/CZ
A/D Conversion Result Lower Register SP
7
6
5
4
3
2
Bit symbol ADRSP1 ADRSP0
⎯
⎯
⎯
⎯
ADREGSPL
Read/Write
R
⎯
⎯
⎯
⎯
(0xFFFF_F310) _{After Reset}
Undefined
⎯
⎯
⎯
⎯
Function
Stores lower 2 bits of A/D
conversion result
1
0
OVRSP ADRSPRF
R
R
0
0
Overrun flag
0: No overrun
occurred
1: Overrun
occurred
A/D conversion
result store flag
1: Conversion
result stored
ADREGSPH
(0xFFFF_F311)
Bit symbol
Read/Write
After Reset
Function
A/D Conversion Result Upper Register SP
7
6
5
4
3
2
ADRSP9 ADRSP8 ADRSP7 ADRSP6 ADRSP5 ADRSP4
R
Undefined
Stores upper 8 bits of A/D conversion result
1
ADRSP3
0
ADRSP2
Converted value for channe ^{9 8 7 6 5 4 3 2 1 0}
x
ADREGxH
765 4 3210
ADREGxL
76543210
Bits 2 to 5 are always read as 1s.
Note1: Bit 0 is the A/D conversion result store flag ADRxRF. This bit is set to 1 when an A/D converted
value is stored in the register pair. This bit is cleared to 0 when the lower register (ADREGxL) is read.
Note2: Bit 1 is the overrun flag OVRx. This bit is set to 1 when the next conversion result is written before
both conversion result registers (ADREGxH and ADREGxL) have been read. Reading the flag
clears the bit.
Figure 3.13.2 A/D Converter Registers (10/12)
A/D Conversion Result Lower Register
7
6
5
4
3
2
1
0
Bit symbol
ADR21 ADR20
⎯
⎯
⎯
⎯
⎯
⎯
ADREGSPL
Read/Write
R/W
⎯
⎯
⎯
⎯
R
R
(0xFFFF_F314) _{After Reset}
Undefined
⎯
⎯
⎯
⎯
0
0
Function
Stores lower 2 bits of A/D
conversion result
ADREGSPH
(0xFFFF_F315)
Bit symbol
Read/Write
After Reset
Function
A/D Conversion Result Compare Upper Register
7
6
5
4
3
2
ADR29 ADR28 ADR27 ADR26 ADR25 ADR24
R/W
0
Stores upper 8 bits of A/D conversion result
1
ADR23
0
ADR22
Note: When setting or modifying a value in these registers, first disable the A/D monitor function by setting
ADMOD3<ADOBSV> to 0.
Figure 3.13.2 A/D Converter Registers (11/12)
TMP1942CY/CZ-320