TA1370FG Datasheet, PDF (30/42 Pages) Toshiba Semiconductor – SYNC Processor, Frequency Counter IC for TV Component Signals

Note
Item
HA08 Clamp pulse phase/width/level
TA1370FG
SW Mode
S07 S23 S24 S26
Test Conditions and Measuring Method (V_CC = 9 V, Ta = 25 ± 3°C, unless otherwise specified)
c
b

 (1) Set sub-address (00) 70.
(2) Input Signal a (horizontal 33.75 kHz) to pin 14 (HD3-IN).
(3) Set sub-address (02) 02.
(4) Measure the clamp pulse phase (CP_S0), width (CP_W0), output level (CP_V0) of pin 15 (CLP-OUT) against
Signal a.
(5) Set sub-address (02) 12.
(6) Measure the clamp pulse phase (CP_S1), width (CP_W1), output level (CP_V1) of pin 15 (SCP-OUT) against
Signal a.
(7) Input no-signal to pin 14.
(8) Measure the clamp pulse phase (CP_S2), width (CP_W2), output level (CP_V2) of pin 15 (SCP-OUT) against pin
16 (HD-OUT).
Signal a
Pin 15 wave form
Pin 16 wave form
Pin 15 wave form
29.63 µs
2.35 µs
1.5 V
CP_S0ï½¥CP_S1
CP_V0ï½¥CP_V1
CP_W0ï½¥CP_W1
CP_S3
CP_V3
CP_W3
30
2003-02-19