TA1370FG Datasheet, PDF (17/42 Pages) Toshiba Semiconductor – SYNC Processor, Frequency Counter IC for TV Component Signals

Data Transmit Format 1
TA1370FG
S Slave address
7 bit
MSB
S: Start condition
0A
Sub address
8 bit
MSB
A: Acknowledge
A Transmit data
8 bit
MSB
AP
P: Stop condition
Data Transmit Format 2
S Slave address 0 A Sub address A Transmit data A ･･････
･･････
Sub address A Transmit data n A P
Data Receive Format
S Slave address
7 bit
MSB
1 A Received data 1 A Received data 2 A P
8 bit
MSB
At the moment of the first acknowledge, the master transmitter becomes a master receiver and the slave
transmitter. This acknowledge is still generated by this slave.
The Stop condition is generated by the master.
(* important) The data read from THIS IC should always be completed in whole two words, not one word,
otherwise the IICBUS may cause error.
Optional Data Transmit Format: Automatic Increment Mode
S Slave address
7 bit
MSB
0A1
MSB
Sub address
7 bit
A Transmit data 1
8 bit
MSB
････ Transmit data 2
8 bit
MSB
AP
In this transmission method, data is set on automatically incremented sub-address from the specified
sub-address.
Purchase of TOSHIBA I²C components conveys a license under the Philips I²C Patent Rights to use these
components in an I²C system, provided that the system conforms to the I²C Standard Specification as
defined by Philips.
17
2003-02-19