TC58NYG1S3EBAI5 Datasheet, PDF (21/65 Pages) Toshiba Semiconductor – MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 GBIT (256M × 8 BIT) CMOS NAND E2PROM

TC58NYG1S3EBAI5
Multi-Page Program Operation with Data Cache Timing Diagram (2/4)
CLE
t_CLS
t_CLS t_CLH
t_CS
CE
t_CS
t_CH
WE
t_ALH
t_ALS
ALE
t_ALH
t_ALS
t_DCBSYW2
t_WB
RE
I/O
RY / BY
t_{DS tDH}
81h
t_DS t_DH
CA0 CA8 PA0 PA8 PA16
to 7 to 11 to 7 to 15
Page Address M
District-1
t_DS
t_DH
D_INN
D_IN
N+1
15h
D_IN2111
t_DS
t_DH
80h
CA0
to 7
Repeat a max of 63 times (in order to program pages 0 to 62 of a block).
1
2
Continued from 1 of last page
: Do not input data while data is being output.
: V_IH or V_IL
21
2011-03-01C