TC58NYG1S3EBAI5 Datasheet, PDF (14/65 Pages) Toshiba Semiconductor – MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 2 GBIT (256M × 8 BIT) CMOS NAND E2PROM

Column Address Change in Read Cycle Timing Diagram (2/2)
TC58NYG1S3EBAI5
CLE
CE
WE
t_{CLS tCLH}
t_CS t_CH
t_RHW
t_WC
t_CLR
t_CLS t_CLH
t_CS
t_CH
tCEA
t_ALH t_ALS
t_ALH t_ALS
ALE
RE
I/O
D_OUT
A+N
RY / BY
t_DS t_DH
05h
t_DS t_DH t_DS t_DH
CA0
CA8
to 7
to 11
Column address
B
t_WHR t_RC
t_DS t_DH
t_IR
E0h
t_REA
D_OUT D_OUT
B B+1
D_OUT
B + N’
Page address
P
Column address
B
1
Continues from 1 of last page
14
2011-03-01C