SSM3J13T_07 Datasheet, PDF (2/6 Pages) Toshiba Semiconductor – Field Effect Transistor Silicon P Channel MOS Type (U-MOSII)

SSM3J13T
Electrical Characteristics (Ta = 25°C)
Characteristics
Gate leakage current
Drain-Source breakdown voltage
Drain Cut-off current
Gate threshold voltage
Forward transfer admittance
Drain-Source ON resistance
Input capacitance
Reverse transfer capacitance
Output capacitance
Switching time
Turn-on time
Turn-off time
Note 3: Pulse test
Symbol
Test Condition
Min Typ. Max Unit
I_GSS
V_GS = ±8 V, V_DS = 0
⎯
⎯
±1
μA
V _{(BR) DSS} I_D = −1 mA, V_GS = 0
−12 ⎯
⎯
V
V _{(BR) DSX} I_D = −1 mA, V_GS = 8 V
−4
⎯
⎯
V
I_DSS
V_DS = −12 V, V_GS = 0
⎯
⎯
−1
μA
V_th
V_DS = −3 V, I_D = −0.1 mA
−0.45 ⎯
−1.1
V
|Y_fs|
V_DS = −3 V, I_D = −1.5 A (Note 3) 3.8
⎯
⎯
S
I_D = −1.5 A, V_GS = −4 V (Note 3) ⎯
50
70
R_{DS (ON)} I_D = −1.5 A, V_GS = −2.5 V (Note 3) ⎯
70
95
mΩ
I_D = −1.5 A, V_GS = −2.0 V (Note 3) ⎯
90 180
C_iss
V_DS = −10 V, V_GS = 0, f = 1 MHz
⎯ 890 ⎯
pF
C_rss
V_DS = −10 V, V_GS = 0, f = 1 MHz
⎯ 203 ⎯
pF
C_oss
V_DS = −10 V, V_GS = 0, f = 1 MHz
⎯ 288 ⎯
pF
t_on
V_DD = −10 V, I_D = −1 A
t_off
V_GS = 0~−2.5 V, R_G = 4.7 Ω
⎯
48
⎯
ns
⎯ 120 ⎯
Switching Time Test Circuit
(a) Test circuit
0
IN
−2.5 V
10 μs
(b) V_IN
OUT
V_DD = −10 V
R_G = 4.7 Ω
D.U. ^<= 1%
V_IN: t_r, t_f < 5 ns
COMMON SOURCE
Ta = 25°C
(c) V_OUT
V_DD
0V
−2.5 V
V_{DS (ON)}
V_DD
10%
90%
90%
10%
t_r
t_f
t_on
t_off
Precaution
V_th can be expressed as voltage between gate and source when low operating current value is I_D = −100 μA
for this product. For normal switching operation, V_{GS (on)} requires higher voltage than V_th and V_{GS (off)}
requires lower voltage than V_th.
(relationship can be established as follows: V_{GS (off)} < V_th < V_{GS (on)})
Please take this into consideration for using the device.
2
2007-11-01