XC6133 Datasheet, PDF (16/28 Pages) Torex Semiconductor – Delay capacitor adjustable voltage detectors with sense pin isolation

XC6133 Series
■OPERATIONAL DESCRIPTION (Continued)
<Release delay time / detect delay time>
The release delay time and detect delay time are determined by the delay resistors (Rp and Rn) and the delay capacitance Cd.
The ratio of the delay resistances (Rp and Rn) is selectable from 5 options. The delay time is adjustable using the combination
of delay resistance and delay capacitance value. (Refer to “Selection Guide”)
The release delay time (tDR) is calculated using Equation (1).
tDR=Rp×Cd×{-ln(1-VTCd1/VIN)}+tDR0 …(1) * ln is the natural logarithm.
The delay capacitance pin threshold voltage is VTCd1=VIN/2(TYP.), and thus when
tDR0 can be neglected, the release delay time can be calculated simply using Equation (2).
tDR=Rp×Cd×[-ln{1-(VIN/2)/VIN}]=Rp×Cd×0.693 …(2)
The detect delay time (tDF) is calculated using Equation (3).
tDF=Rn×Cd×{-ln(VTCd2/VIN)}+tDF0 …(3) * ln is the natural logarithm.
The delay capacitance pin threshold voltage is VTCd2=VIN/2 (TYP.), and thus when
tDF0 can be neglected, the detect delay can be calculated simply using Equation (4).
tDF=Rn×Cd×{-ln(VIN/2)/VIN}=Rn×Cd×0.693 …(4)
Example 2: When type A is selected (Rp：Rn=144kΩ：0Ω), the delay times are as follows:
If Cd is set to 0.1uF,
tDR =144×10³Ã—0.1×10^-6×0.693 =10ms
tDF is the detect delay time (tDFO) when the delay capacitance Cd is not connected.
Example 3: When type B is selected (Rp：Rn=144kΩ：18kΩ) , the delay times are as follows:
If Cd is set to 0.1uF,
tDR=144×10³Ã—0.1×10^-6×0.693=10ms
tDF =18×10³Ã—0.1×10^-6×0.693=1.25ms
(Note 9) The release delay times tDR in Examples 2 and 3 are the values calculated from Equation (2).
(Note 10) The detect delay time tDF in Example 3 is the value calculated from Equation (4).
(Note 11) Note that the delay times will vary depending on the actual capacitance value of the delay capacitance Cd.
＜Manual reset function＞
The Cd/MRB pin can also be used as a manual reset pin.
When the Cd and RESET switch are connected to the Cd/MRB pin (refer to Fig.1), and under the release condition, if the
RESET switch
turns on, then the detect signal is generated at the RESET/RESETB pin forcibly.
For Active Low type (RESETB), under the release condition, if the RESET switch turns on, then the voltage at the RESETB pin
changes from H to L after the detect delay time.
For Active High type (RESET), under the release condition, if the RESET switch turns on, then the voltage at the RESET pin
changes from L to H after the detect delay time.
Under the detect condition, the condition will be kept even if the RESET switch turns on and off.
In the case that either H level or L level is fed to the Cd/MRB pin without the RESET switch, the behavior of the XC6133 follows
the timing chart in Fig. 4.
L level is fed to MRB pin under the detect condition, the RESET switch will be kept.
H level is fed to MRB pin under the detect condition, the RESET switch will be undefined.
Even though the voltage at the VSEN pin changes from a higher voltage than the detect voltage to a lower voltage, as long as H
level is fed to the MRB pin, the release condition is kept.
If H level or L level is fed to the Cd/MRB pin forcibly, then even though Cd is connected to the pin, the XC6133 can’t have any
delay time.
Release voltage:VDF+VHYS
Detect voltage:VDF
VSEN pin voltage:VSEN（MIN.:0V,MAX.:6.0V)
MRB High level voltage:VMRH
Cd pin threshold voltage:VTCd
MRB Low level voltage:VMRL
Cd pin voltage:VCd/MRB (MIN.:VSS,MAX.:VIN)
Release voltage:VDF+VHYS
Detect voltage:VDF
Undefi ned
Output voltage:VRESE TB
(MIN.:VSS,MAX.:VIN(CMOS),Vpull(Nch open drain))
Fig. 4: Manual reset operation using the Cd/MRB pin (VIN=6.0V, Active Low)
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