XC6133 Datasheet, PDF (15/28 Pages) Torex Semiconductor – Delay capacitor adjustable voltage detectors with sense pin isolation

XC6133
Series
■OPERATIONAL DESCRIPTION (Continued)
②The VSEN pin voltage continues to drop, and when it reaches the detect voltage (VSEN=VDF), the Nch transistor for delay
capacitance discharge turns ON, and discharge of the delay capacitance Cd starts through the delay resistor Rn.
The time from VSEN=VDF until VRESETB reaches Low level is the detect delay time tDF (the detect time when the capacitor is not
connected to the Cd/MRB pin is tDF0).The delay capacitance Cd is discharged through the delay resistor Rn when it is above the
threshold voltage of VTCD2. When it is below the threshold voltage of VTCD2, the delay capacitance Cd is discharged faster
through the internal built-in low impedance switch.
③During the time that the VSEN pin voltage is below the detect voltage VDF, the delay capacitance Cd discharges to ground level.
The VSEN pin starts rising again, and during the time until it reaches the release voltage (VSEN<VDF+VHYS), VRESETB holds Low
level.
④The VSEN pin voltage continues to rise, and when it reaches the release voltage (VDF+VHYS), the Nch transistor for delay
capacitance discharge turns OFF, and charging of the delay capacitance Cd through the delay resistor Rp starts.
The delay capacitance Cd is discharged through the delay resistor Rp when it is below the threshold voltage of VTCD1.
When it is above the threshold voltage of VTCD1, the delay capacitance Cd is discharged faster through the internal built-in low
impedance switch.
⑤When the Cd/MRB pin voltage reaches VTCd1, VRESETB changes to High level.
The time from VSEN=VDF+VHYS until the VRESETB logic changes is the release delay time tDR (the release time when the capacitor
is not connected to the Cd/MRB pin is tDR0).
⑥During the time that the VSEN pin voltage is higher than the detect voltage (VSEN>VDF), VRESETB holds High level.
The above operation description is for an Active Low detection product.
For an Active High product, reverse the logic of the reset pin.
<High voltage detection circuit example>
High voltage detects battery voltage (+B) which was divided into R1 and R2.
The calculation method for high voltage detection is given below.
For the circuit schematic, refer to Fig. 3: High voltage detection circuit.
VDF(H)=VDF(T)×{(R1+R2)÷R2}
VHYS(H)=VHYS×{(R1+R2)÷R2}
VDR(H)=VDF(H)+VHYS(H)
Example 1: For detecting 12.0V (+B: Battery voltage), R1=220kΩ and R2=20kΩ are set to divide the battery voltage
and the VSEN pin voltage is set to VDF(T)=1.0V.
The release voltage VDR(T)=1.05V(TYP.) and VHYS=VDR(T) -VDF(T)=0.05V(TYP.) are pre-set inside the IC.
VDF(H)=12.0V
VHYS(H)=0.6V
VDR(H)=12.6V
(Note 1) VDF(H) is the detect voltage after external adjustment.
(Note 2) VHYS(H) is the hysteresis range after external adjustment.
(Note 3) VDR(H) is the release voltage after external adjustment.
(Note 4) VDF(T) is the detect voltage.
(Note 5) VHYS is the hysteresis range inside of the IC.
(Note 6) VDR(T) is the release voltage.
(Note 7) The R2 resistance is in parallel with the internal RSEN resistance, and thus to increase the accuracy of the detect
voltage and release voltage after external adjustment, select an R2 resistance that is sufficiently small with respect to the RSEN
resistance. For RSEN resistance values, refer to SPEC TABLE (p.10).
(Note 8) If high voltage is to be detected, divide the voltage with resistors R1 and R2 so that VSEN pin≦6V.
+B
V_DD
R1
R2
GND
RESET
Cd
SW
VIN
VSEN
RESET
RESETB
Cd/MRB
VSS
Rpull^(*1)
Fig. 3: High Voltage Detection Circuit
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