XC6133 Datasheet, PDF(14/28 Page) Torex Semiconductor – Delay capacitor adjustable voltage detectors with sense pin isolation

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XC6133 Datasheet, PDF (14/28 Pages) Torex Semiconductor – Delay capacitor adjustable voltage detectors with sense pin isolation

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XC6133 Series

â OPERATIONAL DESCRIPTION

Fig. 1 shows a typical block diagram. Fig. 2 shows the timing chart of Fig. 1.

VR or DCDC

VIN

VDD Cd/MRB

RESET Cd

VSEN

RSEN=RA+RB+RC

VREF

DELAY/

MRB

CONTROL

BLOCK

RESETB

VSS

* The XC6133N series (N-ch open drain output) requires a resistor to pull up the output.

Fig. 1: Typical block diagram (Active Low product)

VSEN pin voltage:VSEN(MIN.:0V,MAX.:6.0V)

Release voltage:VDF+VHYS

Detect voltage:VDF

Cd/MRB pin voltage:VCd/MRB(MIN.:VSS,MAX.:VIN)

Cd pin threshold voltage:VTCd1,VTCd2

Output voltage:VRESETB(MIN.:VSS,MAX.:VIN)

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ï½DR

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Fig. 2: Timing chart of Fig. 1(VIN=6.0V, Active Low)

â In the initial state, a voltage that is sufficiently high (MAX.: 6.0V) with respect to the release voltage is applied to the VSEN pin,

and the delay capacitance Cd is charged up to the power input pin voltage.

The VSEN pin voltage starts to fall, and during the time until it reaches the detect voltage (VSEN>VDF), VRESETB is High level (=VIN).

Note: If the pull-up resistor is connected to a power supply other than the power input pin VIN when using the Nch open drain

output (XC6133N), High level will be the voltage of the power supply to which the pull-up resistor is connected.

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