XC6118_1 Datasheet, PDF (12/20 Pages) Torex Semiconductor – Voltage Detector with Separated Sense Pin & Delay Capacitor Pin

XC6118 Series
■OPERATIONAL EXPLANATION (Continued)
④ When the sense pin voltage continues to increase up to the release voltage level (VDF+VHYS), the N-ch transistor (M1) for
the delay capacitance (Cd) discharge will be turned OFF, and the delay capacitance (Cd) will start discharging via a delay
resistor (Rdelay). The inverter (Inv_.1) will operate as a comparator (Rise Logic Threshold: VTLH=VTCD, Fall Logic
Threshold: VTHL=VSS) while the sense pin voltage keeps higher than the detect voltage (VSEN > VDF).
⑤ While the delay capacitance pin voltage (VCD) rises to reach the delay capacitance pin threshold voltage (VTCD) with the
sense pin voltage equal to the release voltage or higher, the sense pin will be charged by the time constant of the RC series
circuit. Assuming the time to the release delay time (t_DR), it can be given by the formula (1).
t_DR=-R_delay×Cd×ln(1-V_TCD/V_IN) …(1)
The release delay time can also be briefly calculated with the formula (2) because the delay resistance is 2.0MΩ(TYP.) and
the delay capacitance pin voltage is VIN /2 (TYP.)
t_DR=R_delay×Cd×0.69 …(2)
*：R_delay is 2.0MΩ（TYP.）
As an example, presuming that the delay capacitance is 0.68μF, t_DR is :
2.0×10⁶×0.68×10^-6×0.69=938(ms)
* Note that the release delay time may remarkably be short when the delay capacitance (Cd) is not discharged to the ground
(=VSS) level because time described in ③ is short.
⑥ When the delay capacitance pin voltage reaches to the delay capacitance pin threshold voltage (VCD=VTCD), the inverter
(Inv.1) will be inverted. As a result, the output voltage changes into the “High” (=VIN) level. t_DR0 is defined as time which
ranges from VSEN=VDF+VHYS to the VOUT of “High” level without connecting to the Cd.
⑦ While the sense voltage is higher than the detect voltage (VSEN > VDF), the delay capacitance pin is charged until the delay
capacitance pin voltage becomes the input voltage level. Therefore, the output voltage maintains the “High”(=VIN) level.
●Function Chart
V_SEN
L
H
Cd
TRANSITION OF V_OUT CONDITION *1
①
②
L
H
L
⇒
L
L
H
H
L
L
⇒
L
H
⇒
L
H
H
⇒
H
*1: VOUT transits from condition ① to ② because of the combination of VSEN and Cd.
●Example
ex. 1) V_OUT ranges from ‘L’ to ‘H’ in case of VSEN = ‘H’ (VDR≧VSEN), Cd=’H’ (VTCD≧Cd) while VOUT is ‘L’.
ex. 2) V_OUT maintains ‘H’ when Cd ranges from ‘H’ to ‘L’, VSEN=’H’ and Cd=’L’ when V_OUT becomes ‘H’ in ex.1.
●Release Delay Time Chart
DELAY
CAPACITANCE [Cd]
(μF)
0.010
0.022
0.047
0.100
0.220
0.470
1.000
RELEASE DELAY TIME [tDR]
(TYP.)
(ms)
13.8
30.4
64.9
138
304
649
1380
* The release delay time values above are calculated by using the formula (2).
*2: The release delay time (t_DR) is influenced by the delay capacitance Cd.
12/20
RELEASE DELAY TIME [tDR] *2
(MIN. ~ MAX.)
(ms)
11.0 ~ 16.6
24.3 ~ 36.4
51.9 ~ 77.8
110 ~ 166
243 ~ 364
519 ~ 778
1100 ~ 1660