XC6118_1 Datasheet, PDF (11/20 Pages) Torex Semiconductor – Voltage Detector with Separated Sense Pin & Delay Capacitor Pin

XC6118
Series
■OPERATIONAL EXPLANATION
A typical circuit example is shown in Figure 1, and the timing chart of Figure 1 is shown in Figure 2.
VIN
VSEN
M2
ＲＳEN=R1+R2+R3
Comparator
R1
Rdelay
M4
Inverter
VIN
VSEN
R2
Vref
M3
M5
M1
R3
Cd
Cd
*The XC6118N series (N-ch open
drain output) requires a pull-up
resistor for pulling up output.
VOUT
VSS
Figure 1: Typical application circuit example
Sense Pin Voltage: V_SEN(MIN.:0V MAX.:6.0V)
Release Voltage: V_DF+V_HYS
Detect Voltage: V_DF
Delay Capacitance Pin Voltage: V_CD(MIN.:V_SS, MAX.:V_IN)
Delay Capacitance Pin Threshold Voltage: V_TCD
Output Voltage Pin Voltage: V_OUT (MIN.:V_SS MAX:V_IN)
Figure 2: The timing chart of Figure 1
① As an early state, the sense pin is applied sufficiently high voltage (6.0V MAX.) and the delay capacitance (Cd) is charged
to the power supply input voltage, (VIN: 1.0V MIN., 6.0V MAX.). While the sense pin voltage (VSEN) starts dropping to
reach the detect voltage (VDF) (VSEN>VDF), the output voltage (VOUT) keeps the “High” level (=VIN).
* If a pull-up resistor of the XC6118N series (N-ch open drain) is connected to added power supply different from the input
voltage pin, the “High” level will be a voltage value where the pull-up resistor is connected.
② When the sense pin voltage keeps dropping and becomes equal to the detect voltage (VSEN =VDF), an N-ch transistor (M1)
for the delay capacitance (Cd) discharge is turned ON, and starts to discharge the delay capacitance (Cd). An inverter
(Inv_.1) operates as a comparator of the reference voltage VIN, and the output voltage changes into the “Low” level (=VSS).
The detect delay time [t_DF] is defined as time which ranges from VSEN=VDF to the VOUT of “Low” level (especially, when the
Cd pin is not connected: t_DF0).
③ While the sense pin voltage keeps below the detect voltage, the delay capacitance (Cd) is discharged to the ground voltage
(=VSS) level. Then, the output voltage maintains the “Low” level while the sense pin voltage increases again to reach the
release voltage (VSEN< VDF +VHYS).
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