LM3S5C51 Datasheet, PDF (991/1266 Pages) Texas Instruments – Stellaris® LM3S5C51 Microcontroller

Stellaris^® LM3S5C51 Microcontroller
OTG A /
Host
OTG B /
Device
Register 323: USB Device RESUME Interrupt Status and Clear (USBDRISC),
offset 0x418
The USBDRISC 32-bit register is the interrupt clear register. On a write of 1, the corresponding
interrupt is cleared. A write of 0 has no effect.
USB Device RESUME Interrupt Status and Clear (USBDRISC)
Base 0x4005.0000
Offset 0x418
Type W1C, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
RESUME
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO R/W1C
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:1
0
Name
reserved
RESUME
Type
Reset Description
RO 0x0000.000 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
R/W1C
0
RESUME Interrupt Status and Clear
Value Description
1 The RESUME bits in the USBDRRIS and USBDRCIM registers
are set, providing an interrupt to the interrupt controller.
0 No interrupt has occurred or the interrupt is masked.
This bit is cleared by writing a 1. Clearing this bit also clears the RESUME
bit in the USBDRCRIS register.
January 23, 2012
991
Texas Instruments-Production Data