LM3S5C51 Datasheet, PDF (962/1266 Pages) Texas Instruments – Stellaris® LM3S5C51 Microcontroller

Universal Serial Bus (USB) Controller
OTG A /
Host
Register 210: USB Receive Control and Status Endpoint 1 High
(USBRXCSRH1), offset 0x117
Register 211: USB Receive Control and Status Endpoint 2 High
(USBRXCSRH2), offset 0x127
Register 212: USB Receive Control and Status Endpoint 3 High
(USBRXCSRH3), offset 0x137
Register 213: USB Receive Control and Status Endpoint 4 High
(USBRXCSRH4), offset 0x147
Register 214: USB Receive Control and Status Endpoint 5 High
(USBRXCSRH5), offset 0x157
Register 215: USB Receive Control and Status Endpoint 6 High
(USBRXCSRH6), offset 0x167
Register 216: USB Receive Control and Status Endpoint 7 High
(USBRXCSRH7), offset 0x177
Register 217: USB Receive Control and Status Endpoint 8 High
(USBRXCSRH8), offset 0x187
Register 218: USB Receive Control and Status Endpoint 9 High
(USBRXCSRH9), offset 0x197
Register 219: USB Receive Control and Status Endpoint 10 High
(USBRXCSRH10), offset 0x1A7
Register 220: USB Receive Control and Status Endpoint 11 High
(USBRXCSRH11), offset 0x1B7
Register 221: USB Receive Control and Status Endpoint 12 High
(USBRXCSRH12), offset 0x1C7
Register 222: USB Receive Control and Status Endpoint 13 High
(USBRXCSRH13), offset 0x1D7
Register 223: USB Receive Control and Status Endpoint 14 High
(USBRXCSRH14), offset 0x1E7
Register 224: USB Receive Control and Status Endpoint 15 High
(USBRXCSRH15), offset 0x1F7
USBRXCSRHn is an 8-bit register that provides additional control and status bits for transfers
through the currently selected receive endpoint.
OTG B /
Device
962
January 23, 2012
Texas Instruments-Production Data