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LM3S5C51 Datasheet, PDF (63/1266 Pages) Texas Instruments – Stellaris® LM3S5C51 Microcontroller | |||
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Stellaris® LM3S5C51 Microcontroller
1.3.8
1.4
design-for-test features such as I/O pin observation and control, scan testing, and debugging. Texas
Instruments replaces the ARM SW-DP and JTAG-DP with the ARM Serial Wire JTAG Debug Port
(SWJ-DP) interface. The SWJ-DP interface combines the SWD and JTAG debug ports into one
module providing all the normal JTAG debug and test functionality plus real-time access to system
memory without halting the core or requiring any target resident code. The SWJ-DP interface has
the following features:
â IEEE 1149.1-1990 compatible Test Access Port (TAP) controller
â Four-bit Instruction Register (IR) chain for storing JTAG instructions
â IEEE standard instructions: BYPASS, IDCODE, SAMPLE/PRELOAD, EXTEST and INTEST
â ARM additional instructions: APACC, DPACC and ABORT
â Integrated ARM Serial Wire Debug (SWD)
â Serial Wire JTAG Debug Port (SWJ-DP)
â Flash Patch and Breakpoint (FPB) unit for implementing breakpoints
â Data Watchpoint and Trace (DWT) unit for implementing watchpoints, trigger resources, and
system profiling
â Instrumentation Trace Macrocell (ITM) for support of printf style debugging
â Trace Port Interface Unit (TPIU) for bridging to a Trace Port Analyzer
Packaging and Temperature
â Industrial-range (-40°C to 85°C) 100-pin RoHS-compliant LQFP package
â Industrial-range (-40°C to 85°C) 108-ball RoHS-compliant BGA package
Hardware Details
Details on the pins and package can be found in the following sections:
â âPin Diagramâ on page 1111
â âSignal Tablesâ on page 1113
â âOperating Characteristicsâ on page 1185
â âElectrical Characteristicsâ on page 1186
â âPackage Informationâ on page 1257
January 23, 2012
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Texas Instruments-Production Data
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