TSB83AA22C_16 Datasheet, PDF (99/115 Pages) Texas Instruments – PHY and OHCI Link Device

www.ti.com
TSB83AA22C IEEE Std 1394b-2002
PHY and OHCI Link Device
SLLS802 – FEBRUARY 2007
Table 6-66. Isochronous Transmit Context Control Register Description
BIT
FIELD NAME
TYPE
DESCRIPTION
31 cycleMatchEnable
RSCU
When bit 31 is set to 1, processing occurs such that the packet described by the context first
descriptor block is transmitted in the cycle whose number is specified in the cycleMatch field
(bits 30–16). The cycleMatch field (bits 30–16) must match the low-order two bits of
cycleSeconds and the 13-bit cycleCount field in the cycle-start packet that is sent or received
immediately before isochronous transmission begins. Because the isochronous transmit DMA
controller can work ahead, the processing of the first descriptor block might begin slightly in
advance of the actual cycle in which the first packet is transmitted.
The effects of this bit, however, are impacted by the values of other bits in this register and
are explained in the 1394 Open Host Controller Interface Specification. Once the context has
become active, hardware clears this bit.
30–16 cycleMatch
RSC
This field contains a 15-bit value, corresponding to the low-order 2 bits of the isochronous
cycle timer register at OHCI offset F0h (see Section 6.2.34, Isochronous Cycle Timer
Register) cycleSeconds field (bits 31–25) and the cycleCount field (bits 24–12). If bit 31
(cycleMatchEnable) is set to 1, this isochronous transmit DMA context becomes enabled for
transmits when the low-order two bits of the isochronous cycle timer register cycleSeconds
field (bits 31–25) and the cycleCount field (bits 24–12) value equal this field (cycleMatch)
value.
15 run
RSC
Bit 15 is set to 1 by software to enable descriptor processing for the context and cleared by
software to stop descriptor processing. The TSB83AA22C device changes this bit only on a
system (hardware) or software reset.
14–13 RSVD
R
Reserved. Bits 14–13 return 0s when read.
12 wake
11⁽¹⁾ dead
RSU
RU
Software sets bit 12 to 1 to cause the TSB83AA22C device to continue or resume descriptor
processing. The TSB83AA22C device clears this bit on every descriptor fetch.
The TSB83AA22C device sets bit 11 to 1 when it encounters a fatal error, and clears the bit
when software clears bit 15 (run) to 0.
10 active
RU The TSB83AA22C device sets bit 10 to 1 when it is processing descriptors.
9–5 RSVD
4–0⁽¹⁾ event code
R
Reserved. Bits 9–5 return 0s when read.
RU Following an OUTPUT_LAST* command, the error code is indicated in this field. Possible
values are: ack_complete, evt_descriptor_read, evt_data_read, and evt_unknown.
(1) On an overflow for each running context, the isochronous transmit DMA supports up to seven cycle skips when the following are true:
• Bit 11 (dead) in either the isochronous transmit or receive context control register is set to 1.
• Bits 4–0 (eventcode field) in either the isochronous transmit or receive context control register is set to evt_timeout.
• Bit 24 (unrecoverableError) in the interrupt event register at OHCI offset 80h/84h (see Section 6.2.21, Interrupt Event Register) is
set to 1.
6.2.43 Isochronous Transmit Context Command Pointer Register
The isochronous transmit context command pointer register contains a pointer to the address of the first
descriptor block that the TSB83AA22C device accesses when software enables an isochronous transmit
context by setting bit 15 (run) in the isochronous transmit context control register (see Section 6.2.42,
Isochronous Transmit Context Control Register) to 1. The isochronous transmit DMA context command
pointer can be read when a context is active. The n value in the following register addresses indicates the
context number (n = 0, 1, 2, 3, …, 7).
Type:
Offset:
Default:
Read only
20Ch + (16 × n)
XXXX XXXXh
Bit
31 30 29 28 27 26 25 24
23
22
21
20
19
18
17
16
Default
XXXXXXX
X
X
X
X
X
X
X
X
X
Bit
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Default
XXXXXXX
X
X
X
X
X
X
X
X
X
Submit Documentation Feedback
TSB83AA22C Link Layer Controller Programming Model
99