TSB83AA22C_16 Datasheet, PDF (59/115 Pages) Texas Instruments – PHY and OHCI Link Device

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TSB83AA22C IEEE Std 1394b-2002
PHY and OHCI Link Device
SLLS802 – FEBRUARY 2007
Table 6-13. CardBus CIS Base Address Register Description
BIT FIELD NAME
31–11 CIS_BASE
10–4 CIS_SZ
3 CIS_PF
2–1 CIS_MEMTYPE
0 CIS_MEM
TYPE
R/W
R
R
R
R
DESCRIPTION
CIS base address. This field specifies the upper 21 bits of the 32-bit CIS base address. If CARDBUS
is sampled high on a G_RST, this field is read only, returning 0s when read.
CIS address space size. This field returns 0s when read, indicating that the CIS space requires a
2K-byte region of memory.
CIS prefetch. Bit 3 returns 0 when read, indicating that the CIS is nonprefetchable. Furthermore, the
CIS is a byte-accessible address space, and either a double word or 16-bit word access yields
indeterminate results.
CIS memory type. This field returns 0s when read, indicating that the CardBus CIS base address
register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space.
CIS memory indicator. This bit returns 0 when read, indicating that the CIS is mapped into system
memory space.
6.1.14 CardBus CIS Pointer Register
The TSB83AA22C device can be configured to support CardBus registers via bit 6 (CARDBUS) in the PCI
miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 6.1.30). If
CARDBUS is low (default), then this register is read-only returning 0s when read. If CARDBUS is high,
then this register contains the pointer to the CardBus card information structure (CIS). See Table 6-14 for
a description of the register contents.
Type:
Offset:
Default:
Read only
28h
0000 000Xh
Bit
31 30 29 28 27 26 25 24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
X
X
X
Table 6-14. CardBus CIS Pointer Register Description
BIT
31–28
27–3
FIELD NAME
ROM_IMAGE
CIS_OFFSET
2–0 CIS_INDICATOR
TYPE
R
R
R
DESCRIPTION
Because the CIS is not implemented as a ROM image, this field returns 0s when read.
This field indicates the offset into the CIS address space where the CIS begins, and bits 7–3 are
loaded from the serial EEPROM field CIS_Offset (7–3). This implementation allows the
TSB83AA22C device to produce serial EEPROM addresses equal to the lower PCI address byte to
acquire data from the serial EEPROM.
This field indicates the address space where the CIS resides and returns 011b if bit 6 (CARDBUS)
in the PCI miscellaneous configuration register is high, then 011b indicates that CardBus CIS base
address register at offset 18h in the PCI configuration header contains the CIS base address. If
CARDBUS is low, this field returns 000b when read.
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TSB83AA22C Link Layer Controller Programming Model
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