TSB83AA22C_16 Datasheet, PDF (92/115 Pages) Texas Instruments – PHY and OHCI Link Device

TSB83AA22C IEEE Std 1394b-2002
PHY and OHCI Link Device
SLLS802 – FEBRUARY 2007
www.ti.com
Table 6-55. Fairness Control Register Description (continued)
BIT FIELD NAME
7–0 pri_req
TYPE
R/W
DESCRIPTION
This field specifies the maximum number of priority arbitration requests for asynchronous request
packets that the link is permitted to make of the PHY section during a fairness interval.
6.2.31 LLC Section Control Register
The LLC section control set/clear register provides the control flags that enable and configure the link core
protocol portions of the TSB83AA22C device. It contains controls for the receiver and cycle timer. See
Table 6-56 for a description of the register contents.
Type:
Offset:
A
Default:
Read/set/clear/update, read/set/clear, read/set, read only
A8h Set register
ACh Clear register
00X0 0X00h
Bit
31 30 29 28 27 26 25 24
23
22
21
20
19
18
17
16
Default
0
0
0
0
0
0
0
0
0
X
X
X
0
0
0
0
Bit
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Default
0
0
0
0
0
X
X
0
0
0
0
0
0
0
0
0
Table 6-56. LLC Section Control Register Description
BIT
FIELD NAME
31–23 RSVD
22 cycleSource
21 cycleMaster
20 CycleTimerEnable
19–11 RSVD
10 RcvPhyPkt
9 RcvSelfID
8–7 RSVD
6 tag1SyncFilterLock
5–0 RSVD
TYPE
R
RSC
RSCU
RSC
R
RSC
RSC
R
RS
R
DESCRIPTION
Reserved. Bits 31–23 return 0s when read.
When bit 22 is set to 1, the cycle timer uses an external source (CYCLEIN) to determine when to
roll over the cycle timer. When this bit is cleared, the cycle timer rolls over when the timer reaches
3072 cycles of the 24.576-MHz clock (125 µs).
When bit 21 is set to 1 and the PHY section has notified the LLC section that PHY section is root,
the TSB83AA22C device generates a cycle-start packet every time the cycle timer rolls over,
based on the setting of bit 22 (cycleSource). When bit 21 is cleared, the OHCI-Lynx accepts
received cycle-start packets to maintain synchronization with the node which is sending them. Bit
21 is automatically cleared when bit 25 (cycleTooLong) in the interrupt event register at OHCI
offset 80h/84h (see Section 6.2.21, Interrupt Event Register) is set to 1. Bit 21 cannot be set to 1
until bit 25 (cycleTooLong) is cleared.
When bit 20 is set to 1, the cycle timer offset counts cycles of the 24.576-MHz clock and rolls over
at the appropriate time, based on the settings of the above bits. When this bit is cleared, the cycle
timer offset does not count.
Reserved. Bits 19–11 return 0s when read.
When bit 10 is set to 1, the receiver accepts incoming PHY packets into the AR request context if
the AR request context is enabled. This bit does not control receipt of self-ID packets.
When bit 9 is set to 1, the receiver accepts incoming self-ID packets. Before setting this bit to 1,
software must ensure that the self-ID buffer pointer register contains a valid address.
Reserved. Bits 8–7 return 0s when read.
When this bit is set to 1, bit 6 (tag1SyncFilter) in the isochronous receive context match register
(see Section 6.2.46, Isochronous Receive Context Match Register) is set to 1 for all isochronous
receive contexts. When this bit is cleared, bit 6 (tag1SyncFilter) in the isochronous receive context
match register has read/write access. This bit is cleared when G_RST is asserted.
Reserved. Bits 5D/PHY_D0 return 0s when read.
6.2.32 Node Identification Register
The node identification register contains the address of the node on which the OHCI-Lynx chip resides,
and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15–6) and
the NodeNumber field (bits 5–0) is referred to as the node ID. See Table 6-57 for a description of the
register contents.
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TSB83AA22C Link Layer Controller Programming Model
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