TSB83AA22C_16 Datasheet, PDF (85/115 Pages) Texas Instruments – PHY and OHCI Link Device

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TSB83AA22C IEEE Std 1394b-2002
PHY and OHCI Link Device
SLLS802 – FEBRUARY 2007
Table 6-48. Interrupt Event Register Description
BIT
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14–10
9
8
7
FIELD NAME
RSVD
vendorSpecific
SoftInterrupt
RSVD
ack_Tardy
PhyRegRcvd
cycleTooLong
unrecoverableError
cycleInconsistent
cycleLost
cycle64Seconds
cycleSynch
Phy
regAccessFail
busReset
selfIDcomplete
selfIDcomplete2
RSVD
lockRespErr
postedWriteErr
isochRx
TYPE
R
RSC
RSC
R
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
RSCU
R
RSCU
RSCU
RU
DESCRIPTION
Reserved. Bit 31 returns 0 when read.
This vendor-specific interrupt event is reported when either of the general-purpose interrupts is
asserted. The general-purpose interrupts are enabled by setting the corresponding bits INT_3EN
and INT_2EN (bits 31 and 23, respectively) to 1 in the GPIO control register at offset FCh in the
PCI configuration space (see Section 6.1.33, GPIO Control Register).
Software interrupt. Bit 29 is used by software to generate a TSB83AA22C interrupt for its own use.
Reserved. Bit 28 returns 0 when read.
Bit 27 is set to 1 when bit 29 (ack_Tardy_enable) in the host controller control register at OHCI
offset 50h/54h (see Section 6.2.16, Host Controller Control Register) is set to 1 and any of the
following conditions occurs:
a. Data is present in the receive FIFO that is to be delivered to the host.
b. The physical response unit is busy processing requests or sending responses.
c. The TSB83AA22C device sent an ack_tardy acknowledgment.
The bit is set to 1 when the TSB83AA22C device has received a PHY section register data byte,
which can be read from bits 23–16 in the PHY section control register at OHCI offset ECh (see
Section 6.2.33, Phy Layer Control Register).
If bit 21 (cycleMaster) in the link control register at OHCI offset E0h/E4h (see Section 6.2.31, LLC
Section Control Register) is set to 1, then this indicates that over 125 µs has elapsed between the
start of sending a cycle-start packet and the end of a subaction gap. Bit 21 (cycleMaster) in the
LLC section control register is cleared by this event.
This event occurs when the TSB83AA22C device encounters any error that forces it to stop
operations on any or all of its subunits, for example, when a DMA context sets its dead bit to 1.
While bit 24 is set to 1, all normal interrupts for the context(s) that caused this interrupt are blocked
from being set to 1.
A cycle start was received that had values for cycleSeconds and cycleCount fields that are
different from the values in bits 31–25 (cycleSeconds field) and bits 24–12 (cycleCount field) in the
isochronous cycle timer register at OHCI offset F0h (see Section 6.2.34, Isochronous Cycle Timer
Register).
A lost cycle is indicated when no cycle_start packet is sent or received between two successive
cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately
follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected
after a cycleSynch event without an intervening cycle start. Bit 22 can be set either when a lost
cycle occurs or when logic predicts that one will occur.
A 1 indicates that the 7^th bit of the cycle second counter has changed.
Indicates that a new isochronous cycle has started. Bit 20 is set to 1 when the low order bit of the
cycle count toggles.
Indicates that the PHY section requests an interrupt through a status transfer.
Indicates that an LLC section register access has failed due to a missing SCLK clock signal from
the PHY section. When a register access fails, bit 18 is set to 1 before the next register access.
A 1 indicates that the PHY section has entered bus-reset mode.
A self-ID packet stream has been received. It is generated at the end of the bus initialization
process. Bit 16 is turned off simultaneously when bit 17 (busReset) is turned on.
Secondary indication of the end of a self-ID packet stream. Bit 15 is set to 1 by the TSB83AA22C
device when it sets bit 16 (selfIDcomplete), and retains its state, independent of bit 17 (busReset).
Reserved. Bits 14–10 return 0s when read.
Indicates that the TSB83AA22C device sent a lock response for a lock request to a serial bus
register, but did not receive an ack_complete.
Indicates that a host bus error occurred while the TSB83AA22C device was trying to write a 1394
write request, which had already been given an ack_complete, into system memory.
Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts have
generated an interrupt. This is not a latched event; it is the logical OR of all bits in the isochronous
receive interrupt event register at OHCI offset A0h/A4h (see Section 6.2.26, Isochronous Receive
Interrupt Event Register) and isochronous receive interrupt mask register at OHCI offset A8h/ACh
(see Section 6.2.24, Isochronous Receive Interrupt Mask Register). The isochronous receive
interrupt event register indicates which contexts have been interrupted.
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TSB83AA22C Link Layer Controller Programming Model
85