TM4C1231D5PZ Datasheet, PDF (982/1161 Pages) Texas Instruments – Universal Asynchronous Receiver/Transmitter Run Mode Clock

Inter-Integrated Circuit (I²C) Interface
Figure 16-11. Master RECEIVE of Multiple Data Bytes
Idle
Write Slave
Address to
I2CMSA
Sequence
may be
omitted in a
Single Master
system
Read I2CMCS
Read I2CMCS
NO _{BUSBSY bit=0?}
YES
Write ---01011
to I2CMCS
BUSY bit=0? _NO
YES
ERROR bit=0? ^NO
Read data from
I2CMDR
Write ---01001 NO
to I2CMCS
Index=m-1?
YES
Write ---00101
to I2CMCS
NO _{ARBLST bit=1?}
YES
Write ---0-100
to I2CMCS
Error Service
Idle
Read I2CMCS
BUSY bit=0?
NO
YES
NO _{ERROR bit=0?}
Error Service
YES
Read data from
I2CMDR
Idle
982
July 16, 2013
Texas Instruments-Production Data