TM4C1231D5PZ Datasheet, PDF (350/1161 Pages) Texas Instruments – Universal Asynchronous Receiver/Transmitter Run Mode Clock

System Control
Register 75: Inter-Integrated Circuit Sleep Mode Clock Gating Control
(SCGCI2C), offset 0x720
The SCGCI2C register provides software the capability to enable and disable the I²C modules in
sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled to
save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
Control Register n SCGCn registers specifically for the watchdog modules and has the same bit
polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the I²C modules. To support
legacy software, the SCGC1 register is available. A write to the SCGC1 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
SCGC1 register can be read back correctly with a read of the SCGC1 register. Software
must use this register to support modules that are not present in the legacy registers.
If software uses this register to write a legacy peripheral (such as I²C0), the write causes
proper operation, but the value of that bit is not reflected in the SCGC1 register. If
software uses both legacy and peripheral-specific register accesses, the
peripheral-specific registers must be accessed by read-modify-write operations that
affect only peripherals that are not present in the legacy registers. In this manner, both
the peripheral-specific and legacy registers have coherent information.
Inter-Integrated Circuit Sleep Mode Clock Gating Control (SCGCI2C)
Base 0x400F.E000
Offset 0x720
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
21
20
19
18
17
16
RO
RO
RO
RO
RO
RO
0
0
0
0
0
0
5
4
3
2
1
0
S5
S4
S3
S2
S1
S0
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
Bit/Field
31:6
5
Name
reserved
S5
Type
RO
R/W
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
I²C Module 5 Sleep Mode Clock Gating Control
Value Description
1
Enable and provide a clock to I²C module 5 in sleep mode.
0
I²C module 5 is disabled.
4
S4
R/W
0
I²C Module 4 Sleep Mode Clock Gating Control
Value Description
1
Enable and provide a clock to I²C module 4 in sleep mode.
0
I²C module 4 is disabled.
350
July 16, 2013
Texas Instruments-Production Data