TM4C1231D5PZ Datasheet, PDF (169/1161 Pages) Texas Instruments – Universal Asynchronous Receiver/Transmitter Run Mode Clock

Tiva^™ TM4C1231D5PZ Microcontroller _{(identical to LM4F112C4QC)}
Bit/Field
8
7
6
5
4
Name
IBUS
MMARV
reserved
MLSPERR
MSTKE
Type
R/W1C
R/W1C
RO
R/W1C
R/W1C
Reset
0
0
0
0
0
Description
Instruction Bus Error
Value Description
0 An instruction bus error has not occurred.
1 An instruction bus error has occurred.
The processor detects the instruction bus error on prefetching an
instruction, but sets this bit only if it attempts to issue the faulting
instruction.
When this bit is set, a fault address is not written to the FAULTADDR
register.
This bit is cleared by writing a 1 to it.
Memory Management Fault Address Register Valid
Value Description
0 The value in the Memory Management Fault Address
(MMADDR) register is not a valid fault address.
1 The MMADDR register is holding a valid fault address.
If a memory management fault occurs and is escalated to a hard fault
because of priority, the hard fault handler must clear this bit. This action
prevents problems if returning to a stacked active memory management
fault handler whose MMADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
Memory Management Fault on Floating-Point Lazy State Preservation
Value Description
0 No memory management fault has occurred during floating-point
lazy state preservation.
1 No memory management fault has occurred during floating-point
lazy state preservation.
This bit is cleared by writing a 1 to it.
Stack Access Violation
Value Description
0 No memory management fault has occurred on stacking for
exception entry.
1 Stacking for an exception entry has caused one or more access
violations.
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the MMADDR register.
This bit is cleared by writing a 1 to it.
July 16, 2013
169
Texas Instruments-Production Data