TMS570LC4357 Datasheet, PDF (97/227 Pages) Texas Instruments – Hercules Microcontroller Based on the ARM® Cortex-R Core

www.ti.com
TMS570LC4357
SPNS195C – FEBRUARY 2014 – REVISED JUNE 2016
6.9.4 Master/Slave Access Privileges
Table 6-26 and Table 6-27 list the access permissions for each bus master on the device. A bus master is
a module that can initiate a read or a write transaction on the device.
Each slave module on either the CPU Interconnect Subsystem or the Peripheral Interconnect Subsystem
is listed in Table 6-27. Allowed indicates that the module listed in the MASTERS column can access that
slave module.
Table 6-26. Bus Master / Slave Access Matrix for CPU Interconnect Subsystem
MASTERS
CPU Read
CPU Write
DMA PortA
POM
PS_SCR_M
ACP_M
L2 Flash OTP, ECC,
Bank 7 (EEPROM)
Allowed
Not allowed
Allowed
Not allowed
Allowed
Not allowed
SLAVES ON CPU INTERCONNECT SUBSYSTEM
L2 FLASH
L2 SRAM
CACHE MEMORY
Allowed
Not allowed
Allowed
Not allowed
Allowed
Not Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Not allowed
Not allowed
Not allowed
Not allowed
EMIF
Allowed
Allowed
Allowed
Allowed
Allowed
Not allowed
Table 6-27. Bus Master / Slave Access Matrix for Peripheral Interconnect Subsystem
MASTER ID TO
PCRx
0
1
2
3
4
5
7
9
10
MASTERS
CPU Read
CPU Write
Reserved
DMA PortB
HTU1
HTU2
FTU
DMM
DAP
EMAC
SLAVES ON PERIPHERAL INTERCONNECT SUBSYSTEM
CRC1/CRC2
Resources Under
PCR2 and PCR3
Resources Under
PCR1
CPU Interconnect
Subsystem SDC
MMR Port (see
Section 6.9.6 )
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
–
–
–
–
Allowed
Allowed
Allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Not allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Allowed
Not allowed
Allowed
Not allowed
Not allowed
6.9.4.1 Special Notes on Accesses to Certain Slaves
By design only the CPU and debugger can have privileged write access to peripherals under the PCR1
segment. The other masters can only read from these registers.
The master-id filtering check is implemented inside each PCR module of each peripheral segment and
can be used to block certain masters from write accesses to certain peripherals. An unauthorized master
write access detected by the PCR will result in the transaction being discarded and an error being
generated to the ESM module.
The device contains dedicated logic to generate a bus error response on any access to a module that is in
a power domain that has been turned off.
Copyright © 2014–2016, Texas Instruments Incorporated
System Information and Electrical Specifications
97
Submit Documentation Feedback
Product Folder Links: TMS570LC4357