TMS570LC4357 Datasheet, PDF (106/227 Pages) Texas Instruments – Hercules Microcontroller Based on the ARM® Cortex-R Core

TMS570LC4357
SPNS195C – FEBRUARY 2014 – REVISED JUNE 2016
www.ti.com
MEMORY
L2RAMW
L2RAMW
R5_ICACHE
R5_DCACHE
Reserved
Reserved
FRAY_TRBUF_MSG
RAM
CPGMAC_CPPI
R5_DCACHE_Dirty
Reserved
Table 6-33. PBIST RAM Grouping (continued)
RAM
GROUP
TEST CLOCK
RGS
RDS
29 GCM_HCLK
1
7
6
1
6
30 GCM_HCLK
11
32
16
21
26
1
6
31 GCM_GCLK1
40
11
16
1
6
11
32 GCM_GCLK1
41
16
21
26
1
6
33 GCM_GCLK2
43
11
16
1
6
11
34 GCM_GCLK2
44
16
21
26
MEM
TYPE
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
SP
NO.
BANKS
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
TEST PATTERN
(ALGORITHM)
TRIPLE
READ
SLOW READ
TRIPLE
READ
FAST READ
March 13N⁽¹⁾
TWO PORT
(cycles)
March 13N⁽¹⁾
SINGLE
PORT
(cycles)
ALGO MASK ALGO MASK ALGO MASK ALGO MASK
0x1
0x2
0x4
0x8
532580
1597740
166600
299820
166600
299820
35 GCM_VCLKP
26 9..11
SP
3
149910
36 GCM_VCLK3
27
7
SP
1
37 GCM_GCLK1
42
2
SP
1
38 -
-
-
-
-
133170
16690
-
Several memory testing algorithms are stored in the PBIST ROM. However, TI only recommends the
March13N algorithm for application testing of RAM.
The PBIST ROM clock frequency is limited to the maximum frequency of 82.5 MHz.
The PBIST ROM clock is divided down from HCLK. The divider is selected by programming the ROM_DIV
field of the Memory Self-Test Global Control Register (MSTGCR) at address 0xFFFFFF58.
106 System Information and Electrical Specifications
Copyright © 2014–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS570LC4357