TMS320DM8148_16 Datasheet, PDF (96/376 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
www.ti.com
3.2.10 I2C
SIGNAL
NAME
I2C[0]_SCL
I2C[0]_SDA
I2C[1]_SCL/
HDMI_SCL
I2C[1]_SDA/
HDMI_SDA
VIN[0]A_FLD/
VIN[0]B_VSYNC/
UART5_RXD/
I2C[2]_SCL/
GP2[1]
VOUT[1]_G_Y_YC[2]/
GPMC_A[13]/
VIN[1]A_D[21]/
HDMI_SCL/
SPI[2]_SCS[2]/
I2C[2]_SCL/
GP3[20]
VIN[0]A_D[16]/
CAM_D[8]/
I2C[2]_SCL/
GP0[10]
UART0_DCD/
UART3_RXD/
SPI[0]_SCS[3]/
I2C[2]_SCL/
SD1_POW/
GP1[2]
NO.
AC4
AB6
AF24
AG24
AA20
AF27
AA21
AH4
Table 3-16. I2C Terminal Functions
TYPE⁽¹⁾ OTHER ^{(2) (3)}
MUXED
DESCRIPTION
I2C[0]
I/O
DVDD
–
PINCNTL263
I2C[0] Clock I/O. For proper device operation,
this pin must be pulled up via external resistor.
I/O
DVDD
–
PINCNTL264
I2C[0] Data I/O. For proper device operation,
this pin must be pulled up via external resistor.
I2C[1]
I/O
DVDD
HDMI
PINCNTL78
DSIS: 1
I2C[1] Clock I/O. For proper device operation in
I2C mode, this pin must be pulled up via
external resistor.
I/O
DVDD
HDMI
PINCNTL79
DSIS: 1
I2C[1] Data I/O. For proper device operation in
I2C mode, this pin must be pulled up via
external resistor.
I2C[2]
VIN[0]A, VIN[0]B,UART5,
I/O
IPU
DVDD
GP2
PINCNTL136
DSIS: 1
MM: MUX3
VOUT[1], GPMC, VIN[1]A,
I/O
IPU
DVDD
HDMI, SPI[2], GP3
PINCNTL228
DSIS: 1
MM: MUX2
I2C[2] Clock I/O. For proper device operation in
I2C mode, this pin must be pulled up via
external resistor.
VIN[0]A, CAM I/F, GP0
I/O
IPU
DVDD_C
PINCNTL156
DSIS: 1
MM: MUX1
UART0, UART3, SPI[0],
I/O
IPU
DVDD
SD1, GP1
PINCNTL74
DSIS: 1
MM: MUX0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal, MM = Multi Muxed, DSIS = De-
selected Input State
(2) IPD = Internal Pulldown Active, IPU = Internal Pullup Active, DIS = Internal Pull Disabled. This represents the default state of the
Internal Pull after Reset. For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown
resistors are required, see Section 4.5.1, Pullup/Pulldown Resistors and the Section 7.3.17, Pin Behaviors at Reset.
(3) Specifies the operating I/O supply voltage for each signal
96
Device Pins
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