TMS320DM8148_16 Datasheet, PDF (33/376 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
www.ti.com
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
Table 2-7. L4 Slow Peripheral Memory Map (continued)
Cortex-A8 and L3 Masters
START
ADDRESS
(HEX)
END ADDRESS
(HEX)
0x481C_E000 0x481C_FFFF
0x481D_0000 0x481D_1FFF
0x481D_2000 0x481D_3FFF
0x481D_4000 0x481D_5FFF
0x481D_6000 0x481D_6FFF
0x481D_7000 0x481D_7FFF
0x481D_8000
0x481E_7FFF
0x481E_8000
0x481E_8FFF
0x481E_9000
0x481F_FFFF
0x4820_0000
0x4820_0FFF
0x4820_1000
0x4823_FFFF
0x4824_0000
0x4824_0FFF
0x4824_1000
0x4827_FFFF
0x4828_0000
0x4828_0FFF
0x4828_1000
0x482F_FFFF
0x4830_0000
0x48FF_FFFF
C674x DSP
START
END ADDRESS
ADDRESS (HEX)
(HEX)
0x081D_4000
0x081D_6000
0x081D_7000
0x081D_5FFF
0x081D_6FFF
0x081D_7FFF
0x081E_9000
0x081F_FFFF
0x0820_1000
0x0823_FFFF
0x0824_1000
0x0827_FFFF
0x0828_1000
0x0830_0000
0x082F_FFFF
0x08FF_FFFF
SIZE
8KB
8KB
8KB
8KB
4KB
4KB
64KB
4KB
52KB
4KB
252KB
4KB
252KB
4KB
508KB
13MB
DEVICE NAME
DCAN0 Support Registers
DCAN1 Peripheral Registers
DCAN1 Support Registers
Reserved
Reserved
Reserved
MMC/SD/SDIO1 Peripheral Registers
MMC/SD/SDIO1 Support Registers
Reserved
Interrupt controller⁽¹⁾
Reserved ⁽¹⁾
MPUSS config register⁽¹⁾
Reserved ⁽¹⁾
Reserved ⁽¹⁾
Reserved ⁽¹⁾
Reserved
(1) These regions decoded internally by the Cortex™-A8 Subsystem and are not physically part of the L4 Slow. They are included here only
for reference when considering the Cortex™-A8 Memory Map. For Masters other than the Cortex-A8 these regions are reserved.
2.12.5 DDR DMM TILER Extended Addressing Map
The TILER includes an additional 4-GBytes of addressing range, enabled by a 33rd address bit, to access
the frame buffer in rotated and mirrored views. shows the details of the TILER Extended Address
Mapping. This entirety of this additional range is only accessible to the HDVPSS and ISS subsystems.
However, other masters can access any one single view through the 512-MB TILER region in the base
4GByte address memory map.
BLOCK NAME
TILER View 0
TILER View 1
TILER View 2
TILER View 3
TILER View 4
TILER View 5
TILER View 6
TILER View 7
Table 2-8. DDR DMM TILER Extended Address Mapping
START ADDRESS
(HEX)
0x1 0000_0000
0x1 2000_0000
END ADDRESS
(HEX)
0x1 1FFF_FFFF
0x1 3FFF_FFFF
SIZE
512MB
512MB
0x1 4000_0000
0x1 5FFF_FFFF
512MB
0x1 6000_0000
0x1 8000_0000
0x1 7FFF_FFFF
0x1 9FFF_FFFF
512MB
512MB
0x1 A000_0000
0x1 C000_0000
0x1 E000_0000
0x1 BFFF_FFFF
0x1 DFFF_FFFF
0x1 FFFF_FFFF
512MB
512MB
512MB
DESCRIPTION
Natural 0° View
0° with Vertical Mirror
View
0° with Horizontal Mirror
View
180° View
90° with Vertical Mirror
View
270° View
90° View
90° with Horizontal Mirror
View
Copyright © 2011–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320DM8148 TMS320DM8147
Device Overview
33