TMS320DM8148_16 Datasheet, PDF (222/376 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
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8.1.3 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data manual do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (Literature Number: SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
8.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals must transition between V_IH and V_IL (or between V_IL and V_IH) in a monotonic
manner.
222 Peripheral Information and Timings
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