TMS320DM8148_16 Datasheet, PDF (311/376 Pages) Texas Instruments – DaVinci Video Processors

TMS320DM8148, TMS320DM8147
www.ti.com
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
8.13.4.2.4.10 VTT
Like VREF, the nominal value of the VTT supply is half the DDR3 supply voltage. Unlike VREF, VTT is
expected to source and sink current, specifically the termination current for the ADDR_CTRL net class
Thevinen terminators. VTT is needed at the end of the address bus and it should be routed as a power
sub-plane. VTT should be bypassed near the terminator resistors.
8.13.4.2.4.11 CK and ADDR_CTRL Topologies and Routing Definition
The CK and ADDR_CTRL net classes are routed similarly and are length matched to minimize skew
between them. CK is a bit more complicated because it runs at a higher transition rate and is differential.
The following subsections show the topology and routing for various DDR3 configurations for CK and
ADDR_CTRL. Only the components shown in the topologies are allowed. Items such as test points and
additional terminations are specifically disallowed. The figures in the following subsections define the
terms for the routing specification detailed in Table 8-75.
Care should be taken to minimize layer transitions during routing. If a layer transition is necessary, it is
better to transition to a layer using the same reference plane. If this cannot be accommodated, ensure
there are nearby ground vias to allow the return currents to transition between reference planes if both
reference planes are ground or DVDD_DDR. Ensure there are nearby bypass capacitors to allow the
return currents to transition between reference planes if one of the reference planes is ground. The goal is
to minimize the size of the return current loops.
8.13.4.2.4.11.1 Four DDR3 Devices
Four DDR3 devices are supported on the DDR EMIF consisting of four x8 DDR3 devices arranged as one
bank (CS). These four devices may be mounted on a single side of the PCB, or may be mirrored in two
pairs to save board space at a cost of increased routing complexity and parts on the backside of the PCB.
8.13.4.2.4.11.2 CK and ADDR_CTRL Topologies, Four DDR3 Devices
Figure 8-58 shows the topology of the CK net classes and Figure 8-59 shows the topology for the
corresponding ADDR_CTRL net classes.
DDR Differential CK Input Buffers
+–
+–
+–
+–
Processor
+
Differential Clock
Output Buffer
–
Clock Parallel
Terminator
Rcp
DDR_1V5
A1
A2
A3
A4
A3
AT
Cac
Rcp
0.1 µF
A1
A2
A3
A4
A3
AT
Routed as Differential Pair
Figure 8-58. CK Topology for Four x8 DDR3 Devices
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Peripheral Information and Timings 311
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