TM4C1290NCZAD Datasheet, PDF (924/1648 Pages) Texas Instruments – Tiva Microcontroller

External Peripheral Interface (EPI)
Bit/Field
15:14
13:12
11:5
4
3:1
0
Name
reserved
CAPWIDTH
reserved
WRWSM
reserved
RDWSM
Type
RO
RW
Reset
0x0
0x2
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
CS2n Inter-transfer Capture Width
Controls the delay between Host-Bus transfers.
Value Description
0x0 Reserved
0x1 1 EPI clock.
0x2 2 EPI clock.
0x3 Reserved
RO
0x00 Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW
0
CS2n Write Wait State Minus One
This bit is used with the WRWS field in EPIHB16CFG3. This field is not
applicable in BURST mode.
Value Description
0 No change in the number of wait state clock cycles programmed
in the in WRWS field in EPIHB16CFG3 register.
1 Wait state value is now:
WRWS - 1
WRWS field is programmed in EPIHB16CFG3.
RO
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
RW
0
CS2n Read Wait State Minus One
This field is used with RDWS field in EPIHB16CFG3. This bit is not
applicable in BURST mode.
Value Description
0 No change in the number of wait state clock cycles programmed
in the RDWS field of EPIHB16CFG3.
1 Wait state value is now:
RDWS - 1
RDWS field is programmed in EPIHB16CFG3.
924
June 18, 2014
Texas Instruments-Production Data