TM4C1290NCZAD Datasheet, PDF (30/1648 Pages) Texas Instruments – Tiva Microcontroller

Table of Contents
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
DMA Channel Request Mask Set (DMAREQMASKSET), offset 0x020 .............................. 700
DMA Channel Request Mask Clear (DMAREQMASKCLR), offset 0x024 ........................... 701
DMA Channel Enable Set (DMAENASET), offset 0x028 ................................................... 702
DMA Channel Enable Clear (DMAENACLR), offset 0x02C ............................................... 703
DMA Channel Primary Alternate Set (DMAALTSET), offset 0x030 .................................... 704
DMA Channel Primary Alternate Clear (DMAALTCLR), offset 0x034 ................................. 705
DMA Channel Priority Set (DMAPRIOSET), offset 0x038 ................................................. 706
DMA Channel Priority Clear (DMAPRIOCLR), offset 0x03C .............................................. 707
DMA Bus Error Clear (DMAERRCLR), offset 0x04C ........................................................ 708
DMA Channel Assignment (DMACHASGN), offset 0x500 ................................................. 709
DMA Channel Map Select 0 (DMACHMAP0), offset 0x510 ............................................... 710
DMA Channel Map Select 1 (DMACHMAP1), offset 0x514 ............................................... 711
DMA Channel Map Select 2 (DMACHMAP2), offset 0x518 ............................................... 712
DMA Channel Map Select 3 (DMACHMAP3), offset 0x51C .............................................. 713
DMA Peripheral Identification 0 (DMAPeriphID0), offset 0xFE0 ......................................... 714
DMA Peripheral Identification 1 (DMAPeriphID1), offset 0xFE4 ......................................... 715
DMA Peripheral Identification 2 (DMAPeriphID2), offset 0xFE8 ......................................... 716
DMA Peripheral Identification 3 (DMAPeriphID3), offset 0xFEC ........................................ 717
DMA Peripheral Identification 4 (DMAPeriphID4), offset 0xFD0 ......................................... 718
DMA PrimeCell Identification 0 (DMAPCellID0), offset 0xFF0 ........................................... 719
DMA PrimeCell Identification 1 (DMAPCellID1), offset 0xFF4 ........................................... 720
DMA PrimeCell Identification 2 (DMAPCellID2), offset 0xFF8 ........................................... 721
DMA PrimeCell Identification 3 (DMAPCellID3), offset 0xFFC ........................................... 722
General-Purpose Input/Outputs (GPIOs) ................................................................................... 723
Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 742
Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 743
Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 744
Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 745
Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 747
Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 748
Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 749
Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 751
Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 753
Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 754
Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 756
Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 757
Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 758
Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 759
Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 760
Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 762
Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 764
Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 765
Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 767
Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 768
Register 21: GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 770
Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 771
Register 23: GPIO ADC Control (GPIOADCCTL), offset 0x530 ............................................................ 773
Register 24: GPIO DMA Control (GPIODMACTL), offset 0x534 ........................................................... 774
30
June 18, 2014
Texas Instruments-Production Data