TM4C1290NCZAD Datasheet, PDF (771/1648 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1290NCZAD Microcontroller
Register 22: GPIO Port Control (GPIOPCTL), offset 0x52C
The GPIOPCTL register is used in conjunction with the GPIOAFSEL register and selects the specific
peripheral signal for each GPIO pin when using the alternate function mode. Most bits in the
GPIOAFSEL register are cleared on reset, therefore most GPIO pins are configured as GPIOs by
default. When a bit is set in the GPIOAFSEL register, the corresponding GPIO signal is controlled
by an associated peripheral. The GPIOPCTL register selects one out of a set of peripheral functions
for each GPIO, providing additional flexibility in signal definition. For information on the defined
encodings for the bit fields in this register, refer to Table 25-5 on page 1569. The reset value for this
register is 0x0000.0000 for GPIO ports that are not listed in the table below.
Note:
If a particular input signal to a peripheral is assigned to two different GPIO port pins, the
signal is assigned to the port with the lowest letter and the assignment to the higher letter
port is ignored. If a particular output signal from a peripheral is assigned to two different
GPIO port pins, the signal will output to both pins. Assigning an output signal from a
peripheral to two different GPIO pins is not recommended.
Important: The table below shows special consideration GPIO pins. Most GPIO pins are configured
as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0,
GPIOPUR=0, and GPIOPCTL=0). Special consideration pins may be programed to a
non-GPIO function or may have special commit controls out of reset. In addition, a
Power-On-Reset (POR) returns these GPIO to their original special consideration state.
Table 10-12. GPIO Pins With Special Considerations
GPIO Pins Default Reset GPIOAFSEL GPIODEN GPIOPDR GPIOPUR GPIOPCTL GPIOCR
State
PC[3:0]
JTAG/SWD
1
PD[7]
GPIO^a
0
PE[7]
GPIO^a
0
1
0
1
0x1
0
0
0
0
0x0
0
0
0
0
0x0
0
a. This pin is configured as a GPIO by default but is locked and can only be reprogrammed by unlocking the
pin in the GPIOLOCK register and uncommitting it by setting the GPIOCR register.
The GPIO commit control registers provide a layer of protection against accidental
programming of critical hardware signals including the GPIO pins that can function as
JTAG/SWD signals and the NMI signal. The commit control process must be followed
for these pins, even if they are programmed as alternate functions other than JTAG/SWD
or NMI; see “Commit Control” on page 735.
Note:
If the device fails initialization during reset, the hardware toggles the TDO output
as an indication of failure. Thus, during board layout, designers should not
designate the TDO pin as a GPIO in sensitive applications where the possibility
of toggling could affect the design.
June 18, 2014
771
Texas Instruments-Production Data