TM4C1290NCZAD Datasheet, PDF (873/1648 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1290NCZAD Microcontroller
Bit/Field
19
18
17
16
15:8
Name
ALEHIGH
WRCRE
RDCRE
BURST
reserved
Type
RW
RW
RW
RW
RO
Reset
1
Description
CS1n ALE Strobe Polarity
This field is used if CSBAUD bit of the EPIHB16CFG2 register is enabled.
Value Description
0 The address latch strobe for CS1n accesses is ALEn (active
Low).
1 The address latch strobe for CS1n accesses is ALE (active
High).
0
CS1n PSRAM Configuration Register Write
Used for the PSRAM configuration registers (CR).
With WRCRE set, the next transaction by the EPI is a write of the CR bit
field in the EPIHBPSRAM register to the configuration register (CR) of
the PSRAM. The WRCRE bit self clears once the write-enabled CRE
access is complete.
Value Description
0 No Action.
1 Start CRE write transaction for CS1n.
0
CS1n PSRAM Configuration Register Read
Used for the PSRAM configuration registers (CR).
With the RDCRE set, the next access is a read of the PSRAM's
Configuration Register (CR). This bit self clears once the CRE access
is complete. The address for the CRE access is located at
EPIHBPSRAM[19:18]. The read data is returned on
EPIHBPSRAM[15:0].
Value Description
0 No Action.
1 Start CRE read transaction for CS1n.
0
CS1n Burst Mode
Burst mode must be used with an ALE which is configured by
programming the CSCFG and CSCFGEXT fields in the EPIHB16CFG2
register. Burst mode must be used in ADMUX, which is set by the MODE
field in EPIHB16CFG2.
Note: Burst mode is optimized for word-length accesses.
Value Description
0 Burst mode is disabled.
1 Burst mode is enabled for CS1n.
0x0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
June 18, 2014
873
Texas Instruments-Production Data