TM4C1233D5PZ Datasheet, PDF (901/1242 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1233D5PZ Microcontroller
Bit/Field
6
5
4
3
2
Name
RXFF
TXFF
RXFE
BUSY
DCD
Type
RO
Reset
0
Description
UART Receive FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0 The receiver can receive data.
1 If the FIFO is disabled (FEN is 0), the receive holding register
is full.
If the FIFO is enabled (FEN is 1), the receive FIFO is full.
RO
0
UART Transmit FIFO Full
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0 The transmitter is not full.
1 If the FIFO is disabled (FEN is 0), the transmit holding register
is full.
If the FIFO is enabled (FEN is 1), the transmit FIFO is full.
RO
1
UART Receive FIFO Empty
The meaning of this bit depends on the state of the FEN bit in the
UARTLCRH register.
Value Description
0 The receiver is not empty.
1 If the FIFO is disabled (FEN is 0), the receive holding register
is empty.
If the FIFO is enabled (FEN is 1), the receive FIFO is empty.
RO
0
UART Busy
Value Description
0 The UART is not busy.
1 The UART is busy transmitting data. This bit remains set until
the complete byte, including all stop bits, has been sent from
the shift register.
This bit is set as soon as the transmit FIFO becomes non-empty
(regardless of whether UART is enabled).
RO
0
Data Carrier Detect
Value Description
0 The U1DCD signal is not asserted.
1 The U1DCD signal is asserted.
This bit is implemented only on UART1 and is reserved for UART0 and
UART2.
June 12, 2014
901
Texas Instruments-Production Data